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Time and Realtime
Verilog uses the time keyword to represent the current simulation time. time is
double the size of an integer (usually 64 bits) and is unsigned. If your model uses a
timescale you can use realtime to store the simulation time and time units. You can
declare variables of type time or realtime in your models for timing checks, or in
any other operations you need to do with time. See Appendix A.
The built in functions $time and $realtime return the current simulation time.
Example 6-11 Declaring Variables of Type time
time t1, t2;
initial begin
#50 t1 = $time;
rt1 = $realtime;
#50 t2 = $time - $t1;
rt2 = $realtime - rt1;
end
realtime rt1, rt2;
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