 Разработка, производство и продажа радиоэлектронной аппаратуры  |
Требуется программист в Зеленограде
- обработка данных с датчиков; ColdFire; 40 тыс. e-mail:jobsmp@pochta.ru |
По процентам - все использовано не более, чем наполовину (см. статистику ниже).
Нутром понимаю, что проблема - в том, что в один FB (FB1) напихано много цепей, но как из размазать по другим местам - не знаю.
Основной вопрос - почему очень много упало в FB1.
Спасибо !
Ниже приведены куски отчетов - 1: конец лога при трансляции, 2: начало лога по фиттингу, включая статистику по Ф.блоку №1.
Если поможет - могу прислать проект целиком.
Лог: (конец файла)
Optimizer/Partitioner: version C.16
(c) Copyright 1989-1997 Xilinx Inc. All rights reserved.
WARNING:nd201 - Removing unused input(s) '\$Net00144_, \$Net00143_, RSVD3,
RSVD2, RSVD1, RSVD7, RSVD9, RSVD8, RSVD4, RSVD6, RSVD5'. The input(s) are
unused after optimization.
Considering device XC95288XL-PQ208.
Flattening design..
Timing optimization........................................................................................................................................................................................................
Timing driven global resource optimization General global resource optimization........
Re-checking device resources ...
Mapping a total of 128 equations into 16 function blocks....................................
ERROR:hi301 - Cannot fit the design into any of the specified devices.
You may want to decrease the pterm limit for a denser fit, or split the
design into sub-designs, or try a larger device.
А здесь - начало лог файла по фиттингу:
XACT: version C.16 Xilinx Inc.
Fitter Report
Design Name: dmcons
Fitting Status: Did NOT Fit Date: 2-27-2007, 8:21PM
**************************** Resource Summary ****************************
Design Device Macrocells Product Terms Pins
Name Used Used Used Used
dmcons XC95288XL-10-PQ208 128/288 ( 44%) 469/1440 ( 32%) 144/168 ( 85%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 23 23 | I/O : 138 22
Output : 65 65 | GCK/IO : 2 1
Bidirectional : 56 56 | GTS/IO : 3 1
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 144 144
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 128 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 128 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:nd201 - Removing unused input(s) '\$Net00144_, \$Net00143_, RSVD3,
RSVD2, RSVD1, RSVD7, RSVD9, RSVD8, RSVD4, RSVD6, RSVD5'. The input(s) are
unused after optimization.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
ADDR<0> 2 2 FB16_18 STD (b) (b)
ADDR<1> 2 2 FB16_16 STD (b) (b)
ADDR<2> 2 2 FB16_13 STD (b) (b)
ADDR<3> 2 2 FB5_18 STD (b) (b)
ADDR<4> 2 2 FB5_17 STD 61 I/O I
ADDR<5> 2 2 FB5_16 STD (b) (b)
AUXO<13> 3 6 FB3_18 STD (b) (b)
CF_ACT 3 6 FB1_14 STD FAST 35 I/O O
CF_ON 3 6 FB4_8 STD FAST 7 GTS/I/O O
DDR1 3 6 FB4_2 STD FAST 3 GTS/I/O O
DDR10 3 6 FB8_10 STD FAST 192 I/O O
DDR11 3 6 FB10_15 STD FAST 183 I/O O
DDR12 3 6 FB8_2 STD FAST 186 I/O O
DDR13 3 6 FB10_12 STD FAST 180 I/O O
DDR14 3 6 FB10_14 STD FAST 182 I/O O
DDR15 3 6 FB10_3 STD FAST 171 I/O O
DDR16 3 6 FB10_6 STD FAST 174 I/O O
DDR17 3 6 FB12_17 STD FAST 169 I/O O
DDR18 3 6 FB10_2 STD FAST 170 I/O O
DDR19 3 6 FB12_8 STD FAST 162 I/O O
DDR2 3 6 FB4_3 STD FAST 4 I/O O
DDR20 3 6 FB12_11 STD FAST 165 I/O O
DDR21 3 6 FB12_5 STD FAST 160 I/O O
DDR22 3 6 FB12_6 STD FAST 161 I/O O
DDR23 3 6 FB14_12 STD FAST 151 I/O O
DDR24 3 6 FB14_15 STD FAST 154 I/O O
DDR25 3 6 FB15_14 STD FAST 126 I/O O
DDR26 3 6 FB15_15 STD FAST 127 I/O O
DDR27 3 6 FB15_5 STD FAST 119 I/O O
DDR28 3 6 FB15_8 STD FAST 121 I/O O
DDR29 3 6 FB15_2 STD FAST 117 I/O O
DDR3 3 6 FB6_8 STD FAST 201 I/O O
DDR30 3 6 FB15_3 STD FAST 118 I/O O
DDR31 3 6 FB13_10 STD FAST 111 I/O O
DDR32 3 6 FB13_12 STD FAST 113 I/O O
DDR33 3 6 FB13_6 STD FAST 109 I/O O
DDR34 3 6 FB13_8 STD FAST 110 I/O O
DDR35 3 6 FB11_14 STD FAST 100 I/O O
DDR36 3 6 FB11_17 STD FAST 102 I/O O
DDR37 3 6 FB11_11 STD FAST 97 I/O O
DDR38 3 6 FB11_12 STD FAST 99 I/O O
DDR39 3 6 FB11_2 STD FAST 87 I/O O
DDR4 3 6 FB6_12 STD FAST 203 I/O O
DDR40 3 6 FB11_5 STD FAST 89 I/O O
DDR41 3 6 FB9_15 STD FAST 85 I/O O
DDR42 3 6 FB9_17 STD FAST 86 I/O O
DDR43 3 6 FB9_6 STD FAST 77 I/O O
DDR44 3 6 FB9_10 STD FAST 80 I/O O
DDR45 3 6 FB9_3 STD FAST 75 I/O O
DDR46 3 6 FB9_5 STD FAST 76 I/O O
DDR47 3 6 FB7_10 STD FAST 69 I/O O
DDR48 3 6 FB7_14 STD FAST 71 I/O O
DDR5 3 6 FB6_5 STD FAST 199 I/O O
DDR6 3 6 FB6_3 STD FAST 198 I/O O
DDR7 3 6 FB8_12 STD FAST 193 I/O O
DDR8 3 6 FB8_15 STD FAST 195 I/O O
DDR9 3 6 FB8_8 STD FAST 191 I/O O
DDRRSV 3 6 FB14_2 STD FAST 144 I/O O
HAD0 9 14 FB1_5 STD FAST 30 I/O I/O
HAD1 9 14 FB1_2 STD FAST 28 I/O I/O
HAD2 9 14 FB2_15 STD FAST 23 I/O I/O
HAD3 9 14 FB2_14 STD FAST 22 I/O I/O
HAD4 9 14 FB2_17 STD FAST 25 I/O I/O
HAD5 9 14 FB1_3 STD FAST 29 I/O I/O
HAD6 9 14 FB1_6 STD FAST 31 I/O I/O
HAD7 9 14 FB1_8 STD FAST 32 I/O I/O
HMISO 1 1 FB4_15 STD FAST 12 I/O O
IDE_ON 3 6 FB4_10 STD FAST 8 I/O O
IO1 4 7 FB6_15 STD FAST 206 GSR/I/O I/O
IO10 4 7 FB8_6 STD FAST 189 I/O I/O
IO11 4 7 FB8_3 STD FAST 187 I/O I/O
IO12 4 7 FB10_17 STD FAST 185 I/O I/O
IO13 4 7 FB10_10 STD FAST 178 I/O I/O
IO14 4 7 FB10_11 STD FAST 179 I/O I/O
IO15 4 7 FB10_8 STD FAST 175 I/O I/O
IO16 4 7 FB10_5 STD FAST 173 I/O I/O
IO17 4 7 FB12_14 STD FAST 167 I/O I/O
IO18 4 7 FB12_15 STD FAST 168 I/O I/O
IO19 4 7 FB12_12 STD FAST 166 I/O I/O
IO2 4 7 FB6_17 STD FAST 208 I/O I/O
IO20 4 7 FB12_10 STD FAST 164 I/O I/O
IO21 4 7 FB12_2 STD FAST 158 I/O I/O
IO22 4 7 FB12_3 STD FAST 159 I/O I/O
IO23 4 7 FB14_17 STD FAST 155 I/O I/O
IO24 4 7 FB14_14 STD FAST 152 I/O I/O
IO25 4 7 FB15_11 STD FAST 123 I/O I/O
IO26 4 7 FB15_12 STD FAST 125 I/O I/O
IO27 4 7 FB15_10 STD FAST 122 I/O I/O
IO28 4 7 FB15_6 STD FAST 120 I/O I/O
IO29 4 7 FB13_15 STD FAST 115 I/O I/O
IO3 4 7 FB6_14 STD FAST 205 I/O I/O
IO30 4 7 FB13_17 STD FAST 116 I/O I/O
IO31 4 7 FB13_14 STD FAST 114 I/O I/O
IO32 4 7 FB13_11 STD FAST 112 I/O I/O
IO33 4 7 FB13_3 STD FAST 106 I/O I/O
IO34 4 7 FB13_5 STD FAST 107 I/O I/O
IO35 4 7 FB13_2 STD FAST 103 I/O I/O
IO36 4 7 FB11_15 STD FAST 101 I/O I/O
IO37 4 7 FB11_8 STD FAST 91 I/O I/O
IO38 4 7 FB11_10 STD FAST 95 I/O I/O
IO39 4 7 FB11_6 STD FAST 90 I/O I/O
IO4 4 7 FB6_10 STD FAST 202 I/O I/O
IO40 4 7 FB11_3 STD FAST 88 I/O I/O
IO41 4 7 FB9_12 STD FAST 83 I/O I/O
IO42 4 7 FB9_14 STD FAST 84 I/O I/O
IO43 4 7 FB9_11 STD FAST 82 I/O I/O
IO44 4 7 FB9_8 STD FAST 78 I/O I/O
IO45 4 7 FB7_17 STD FAST 73 I/O I/O
IO46 4 7 FB9_2 STD FAST 74 I/O I/O
IO47 4 7 FB7_15 STD FAST 72 I/O I/O
IO48 4 7 FB7_12 STD FAST 70 I/O I/O
IO5 4 7 FB6_2 STD FAST 197 I/O I/O
IO6 4 7 FB6_6 STD FAST 200 I/O I/O
IO7 4 7 FB8_17 STD FAST 196 I/O I/O
IO8 4 7 FB8_14 STD FAST 194 I/O I/O
IO9 4 7 FB8_5 STD FAST 188 I/O I/O
IORSV 3 6 FB16_17 STD FAST 143 I/O O
NOV53 4 7 FB3_15 STD FAST 47 I/O O
NOV_ACT 3 6 FB4_5 STD FAST 5 GTS/I/O O
NOV_ON 3 6 FB4_6 STD FAST 6 I/O O
SD_ACT 3 6 FB14_3 STD FAST 145 I/O O
SD_MOSI 1 1 FB14_8 STD FAST 148 I/O O
SD_SCK 1 1 FB14_11 STD FAST 150 I/O O
SD_SS 3 6 FB14_6 STD FAST 147 I/O O
UDS_ACT 3 6 FB16_15 STD FAST 142 I/O O
UDS_ON 3 6 FB16_14 STD FAST 140 I/O O
ZIF_ACT 3 6 FB3_14 STD FAST 46 GCK/I/O O
ZIF_ON 3 6 FB3_12 STD FAST 45 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
HALE FB2_12 21 I/O I
HMOSI FB2_2 15 I/O I
HSCK FB2_5 17 I/O I
NOV55 FB3_17 48 I/O I
NOV56 FB5_2 49 I/O I
NOV57 FB5_3 50 I/O I
NOV58 FB5_5 51 I/O I
NOV59 FB5_6 54 I/O I
NOV60 FB5_8 55 GCK/I/O I
NOV61 FB5_10 56 I/O I
NOV62 FB5_12 57 I/O I
NOV63 FB5_14 58 I/O I
NOV64 FB5_15 60 I/O I
NOV65 FB5_17 61 I/O I
NOV66 FB7_2 62 I/O I
NOV67 FB7_3 63 I/O I
NOV68 FB7_5 64 I/O I
NOV69 FB7_6 66 I/O I
NOV70 FB7_8 67 I/O I
SD_MISO FB14_10 149 I/O I
\$Net00142_ FB2_8 19 I/O I
\$Net00285_ FB1_12 34 I/O I
\$Net00286_ FB3_8 43 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 49 49 48 1/5 10
FB2 3 30 30 27 0/3 10
FB3 4 10 10 13 3/0 10
FB4 7 11 11 19 7/0 10
FB5 3 4 4 6 0/0 10
FB6 10 18 18 36 4/6 10
FB7 5 12 12 18 2/3 10
FB8 10 17 17 35 5/5 10
FB9 11 17 17 38 6/5 11
FB10 11 18 18 38 6/5 11
FB11 11 17 17 38 6/5 11
FB12 11 18 18 39 5/6 11
FB13 11 20 20 40 4/7 11
FB14 9 15 15 25 7/2 11
FB15 10 16 16 34 6/4 11
FB16 6 10 10 15 3/0 11
---- ----- ----- -----
128 469 65/56 168
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 49/5
Number of signals used by logic mapping into function block: 49
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB1_1 (b) (b)
HAD1 9 8<- \/4 0 FB1_2 STD 28 I/O I/O
HAD5 9 4<- 0 0 FB1_3 STD 29 I/O I/O
(unused) 0 0 \/4 1 FB1_4 (b) (b)
HAD0 9 4<- 0 0 FB1_5 STD 30 I/O I/O
HAD6 9 4<- 0 0 FB1_6 STD 31 I/O I/O
(unused) 0 0 /\4 1 FB1_7 (b) (b)
HAD7 9 4<- 0 0 FB1_8 STD 32 I/O I/O
(unused) 0 0 /\4 1 FB1_9 (b) (b)
(unused) 0 0 0 5 FB1_10 33 I/O
(unused) 0 0 0 5 FB1_11 (b)
(unused) 0 0 0 5 FB1_12 34 I/O I
(unused) 0 0 0 5 FB1_13 (b)
CF_ACT 3 0 0 2 FB1_14 STD 35 I/O O
(unused) 0 0 0 5 FB1_15 36 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 37 I/O
(unused) 0 0 \/3 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: "ADDR<0>" 18: IO25 34: IO7
2: "ADDR<1>" 19: IO26 35: IO8
3: "ADDR<2>" 20: IO30 36: IO9
4: "ADDR<3>" 21: IO31 37: NOV55
5: "ADDR<5>" 22: IO32 38: NOV56
6: HAD3 23: IO33 39: NOV60
7: IO1 24: IO34 40: NOV61
8: IO10 25: IO38 41: NOV62
9: IO14 26: IO39 42: NOV63
10: IO15 27: IO40 43: NOV64
11: IO16 28: IO41 44: NOV68
12: IO17 29: IO42 45: NOV69
13: IO18 30: IO46 46: NOV70
14: IO2 31: IO47 47: "\$Net00142_"
15: IO22 32: IO48 48: "\$Net00285_"
16: IO23 33: IO6 49: "\$Net00286_"
17: IO24
Signal 1 2 3 4 5 Signals FB
Name 0----+----0----+----0----+----0----+----0----+----0 Used Inputs
HAD1 XXX.X..X....XX....X....X....X........X....X...XX.. 14 14
HAD5 XXX.X...X.....X....X....X....X..X.....X....X..XX.. 14 14
HAD0 XXX.X.X....X.....X....X....X.......XX....X....XX.. 14 14
HAD6 XXX.X....X.....X....X....X....X..X.....X....X.XX.. 14 14
HAD7 XXX.X.....X.....X....X....X....X..X.....X....XXX.. 14 14
CF_ACT XXXX.X..........................................X. 6 6
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
