When you compile a design in the Quartus II software, all I/O ports are directly mapped to a pin on the targeted device. This I/O port mapping may create problems for a modular/hierarchical design because lowerlevel modules may have more I/O ports than pins available on the targeted device. Many of these I/O ports will not directly feed into a device pin, but are used to drive internal nodes. The Quartus II software supports virtual pins to accommodate this situation. Virtual pin assignments direct the Quartus II software which I/O ports of the design module become internal nodes in the top-level design. These assignments prevent the number of I/O ports in the lower-level module from exceeding the total number of available device pins.