module leds (clock, nReset, in, out);
input clock, nReset;
input [3:0] in;
output reg [23:0] out;
reg [4:0] cnt;
always @(posedge clock or negedge nReset)
if (!nReset)
cnt <= 5'd0;
else if ((in[0] | in[1]) ? (cnt == 5'd23) : (cnt[4:3]==2'b10))
cnt <= 5'd0;
else
cnt <= cnt + ((in[0] | in[1]) ? 5'b00001 : 5'b01000);
always @(posedge clock)
begin
if (in[0]) out <= 24'h000001 << cnt;
if (in[1]) out <= 24'h800000 >> cnt;
if (in[2]) out <= 24'h0000FF << {cnt[4:3], 3'h0 };
if (in[3]) out <= 24'hFF0000 >> {cnt[4:3], 3'h0 };
end
endmodule