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-- Synopsys, Inc., FPGA
--
-- File name : mult_hdl.vhd
-- Descriprion: HDL inference example (Multiplier)
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port(
a, b : in std_logic_vector(7 downto 0);
prod : out std_logic_vector(15 downto 0)
);
end mult;
architecture behav of mult is
begin -- behav
prod <= a*b;
end behav;
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