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В AHDL не силен, пишу VHDL.
Счетчик считает от макисума вниз, при фронте на входном сигнале возвращается в максимум. LED горит тогда, когда на счетчике не ноль.
--------------------------------------------------------------------------
-- --
-- Watch Dog Timer testbench --
-- --
--------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity WDT is
port (
RESET : in std_logic;
CLOCK : in std_logic;
INPUT : in std_logic;
OUTPUT :out std_logic
);
end WDT;
architecture rtl of WDT is
type tState is (Idle, Work);
signal State : tState;
signal INPUT_d : std_logic;
signal INPUT_dd : std_logic;
signal INPUT_edge_pulse : std_logic;
signal Counter : std_logic_vector(7 downto 0);
begin
-- opredelyaem front vhodnogo signala
process(RESET, CLOCK)
begin
if RESET = '1' then
INPUT_d <= '0';
INPUT_dd <= '0';
elsif rising_edge(CLOCK) then
INPUT_d <= INPUT;
INPUT_dd <= INPUT_d;
end if;
end process;
-- impuls, voznikauschii pri fronte INPUT
INPUT_edge_pulse <= INPUT_d xor INPUT_dd;
-- state machine
process(RESET, CLOCK)
begin
if RESET = '1' then
State <= Idle;
Counter <= "00000000";
elsif rising_edge(CLOCK) then
case State is
when Idle =>
if INPUT_edge_pulse = '1' then
State <= Work;
Counter <= "11111010"; -- 250d
else
State <= Idle;
Counter <= "00000000";
end if;
when Work =>
if Counter = "00000000" then
State <= Idle;
else
State <= Work;
if INPUT_edge_pulse = '1' then
Counter <= "11111010"; -- 250d
else
Counter <= Counter - '1';
end if;
end if;
end case;
end if;
end process;
-- LED gorit kogta schetchik v nule
OUTPUT <= '1' when Counter = "00000000" else '0';
end rtl;
---------------------------------------------------------------
-- и тест
---------------------------------------------------------------
--------------------------------------------------------------------------
-- --
-- Watch Dog Timer --
-- --
--------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity WDT_tb is
end WDT_tb;
architecture tb of WDT_tb is
component WDT
port (
RESET : in std_logic;
CLOCK : in std_logic;
INPUT : in std_logic;
OUTPUT :out std_logic
);
end component;
signal RESET : std_logic:='1';
signal CLOCK : std_logic:='0';
signal INPUT : std_logic:='0';
signal OUTPUT: std_logic;
begin
RESET <= '0' after 100 ns;
CLOCK <= not CLOCK after 10 ns;
INPUT <= '1' after 250 ns,
'0' after 3000 ns,
'1' after 3500 ns,
'0' after 3700 ns,
'1' after 8000 ns,
'0' after 10000 ns,
'1' after 11300 ns,
'0' after 14000 ns,
'1' after 15500 ns,
'0' after 25000 ns,
'1' after 35000 ns,
'0' after 38000 ns,
'1' after 41500 ns;
DUT: WDT
port map(
RESET => RESET,
CLOCK => CLOCK,
INPUT => INPUT,
OUTPUT => OUTPUT
);
end tb;
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