Читаем: Douglas Smith "HDL Chip Design" и хелпы на синтезатор.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;...
architecture arch of ... is
begin
-- asynchronous reset
asyn_p: process (Reset, Clk) is
begin
if (Reset = '1') then
rreg <= '0';
elsif rising_edge(Clk) then
rreg <= iinnppuutt;
end if;
end process asyn_p;
-- synchronous reset (clear)
syn_p: process (Clk) is
begin
if rising_edge(Clk) then
if (Clear = '1') then
rreg <= '0';
else
rreg <= iinnppuutt;
end if;
end process syn_p;
end architecture arch;