module adder
(input clk, reset, input [3:0] addr, input [24:0] din, output [24:0] dout);
wire we;
wire [24:0] sumn, sum;
ram_infer rams(clk, we, addr, sum, sumn);
assign sum = sumn + din;
always @(clk) begin
we <= (clk) ? 1'b1: 1'b0;
end
assign dout = sumn;
endmodule
module ram_infer
#(parameter n = 8)
( input clk, we, input [3:0] a, input [24:0] d, output[24:0] q);
reg [3:0] read_add;
reg [24:0] mem [n-1:0];
always @(posedge clk) begin
if (we)
mem[a] <= d;
read_add <= a;
end
assign q = mem[read_add];
endmodule
Получил:
Total logic elements 361
Total memory bits 0
