SUBDESIGN buf
(
A[WIDTH-1..0] : BIDIR;
B[WIDTH-1..0] : BIDIR;
clk1,clk2, out1, out2 : INPUT;
)
VARIABLE
AA[WIDTH-1..0],BB[WIDTH-1..0] : TRI;
REGA[WIDTH-1..0], REGB[WIDTH-1..0] : DFFE;
OEA, OEB : NODE;
BEGIN
AA[].IN = REGB[].Q;
BB[].IN = REGA[].Q;
REGA[].IN = B[];
REGB[].IN = A[];
REG1[].clk = clk1;
REG2[].clk = clk2;
A[] = AA[].OUT;
B[] = BB[].OUT;
CASE (outA,outB) IS
WHEN B"00" => OEA = GND; OEB = GND; --- Запираем все
WHEN B"01" => OEA = VCC; OEB = GND; --- работает выход A
WHEN B"10" => OEA = GND; OEB = VCC; --- работает выход B
WHEN B"11" => OEA = GND; OEB = GND; --- Запираем все
END CASE;
BB[].OE = OEB;
AA[].OE = OEA;
END;
как-то так вроде