module Modif_I(
input clk,
input [7:0] Din,
input [7:0] Dmod,

output [7:0] Dout
);

reg [7:0] tmpA, tmpB;

assign Dout = clk ? tmpA : tmpB;

always@(posedge clk) tmpA <= Din;

always@(negedge clk) tmpB <= tmpA | Dmod; // <<<< Example of updating


endmodule


/*
module Modif_II(
input clk,
input [7:0] Din,
input [7:0] Dmod,

output reg [7:0] Dout
);

reg [7:0] tmp;

always@(posedge clk) tmp <= Din;

always@(negedge clk) Dout <= tmp | Dmod; // <<<< Example of updating


endmodule