Вот пример. Не помню откуда.
module sqrt
(
input [7:0] radical,
output reg [3:0] q,
output reg [4:0] remainder
);

always @(radical)
begin: sqrt
integer i;
// tt is delta for adding one bit
// v is current sqrt value
reg [7:0] v, remain_der, tt;

v = 0;
remain_der = radical;
for(i = 3; i >= 0; i = i - 1) begin
tt = (v << (i + 1)) | (8'h01 << (i + i));
if(tt <= remain_der) begin
v = v | (8'h01 << i);
remain_der = remain_der - tt;
end
end
q = v[3:0];
remainder = remain_der[4:0];
end

endmodule