Все входы и выходы на схеме я вроде обзывал латиницей..
Ошибки такие:
name "2" in design file xx.vhd contains illegal characters for VHDL
name "3" in design file xx.vhd contains illegal characters for VHDL
name "1" in design file xx.vhd contains illegal characters for VHDL

Вот содержание файла (xx.vhd), на который ругается quartus:

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition"

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY prim1 IS
port
(
wren : IN STD_LOGIC;
Clk1 : IN STD_LOGIC;
Rasr : IN STD_LOGIC;
Zaver : IN STD_LOGIC;
wrenY : IN STD_LOGIC;
RasrVuch : IN STD_LOGIC;
RasrUmnozh : IN STD_LOGIC;
razreshSumm : IN STD_LOGIC;
uprdel : IN STD_LOGIC;
Adr : IN STD_LOGIC_VECTOR(4 downto 0);
AdrY : IN STD_LOGIC_VECTOR(4 downto 0);
Const : IN STD_LOGIC_VECTOR(7 downto 0);
delit : IN STD_LOGIC_VECTOR(15 downto 0);
x : IN STD_LOGIC_VECTOR(7 downto 0);
y : IN STD_LOGIC_VECTOR(7 downto 0);
cov : OUT STD_LOGIC_VECTOR(15 downto 0);
Del1 : OUT STD_LOGIC_VECTOR(7 downto 0);
Del1Y : OUT STD_LOGIC_VECTOR(7 downto 0);
Del2 : OUT STD_LOGIC_VECTOR(7 downto 0);
Del2Y : OUT STD_LOGIC_VECTOR(7 downto 0);
kon : OUT STD_LOGIC_VECTOR(7 downto 0);
konY : OUT STD_LOGIC_VECTOR(7 downto 0);
ost : OUT STD_LOGIC_VECTOR(15 downto 0);
summa : OUT STD_LOGIC_VECTOR(15 downto 0);
Umnozh : OUT STD_LOGIC_VECTOR(15 downto 0);
vix : OUT STD_LOGIC_VECTOR(7 downto 0);
VixAc : OUT STD_LOGIC_VECTOR(7 downto 0);
VixAcY : OUT STD_LOGIC_VECTOR(7 downto 0);
vixY : OUT STD_LOGIC_VECTOR(7 downto 0);
VuhVuch : OUT STD_LOGIC_VECTOR(7 downto 0);
VuhVuchY : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END prim1;

ARCHITECTURE bdf_type OF prim1 IS

attribute black_box : boolean;
attribute noopt : boolean;

component inhb_0
PORT(2 : IN STD_LOGIC;
3 : IN STD_LOGIC;
1 : OUT STD_LOGIC);
end component;
attribute black_box of inhb_0: component is true;
attribute noopt of inhb_0: component is true;

component inhb_1
PORT(2 : IN STD_LOGIC;
3 : IN STD_LOGIC;
1 : OUT STD_LOGIC);
end component;
attribute black_box of inhb_1: component is true;
attribute noopt of inhb_1: component is true;

component lpm_ram_dq0
PORT(wren : IN STD_LOGIC;
clock : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(4 downto 0);
data : IN STD_LOGIC_VECTOR(7 downto 0);
q : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;

component lpm_mult0
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(7 downto 0);
datab : IN STD_LOGIC_VECTOR(7 downto 0);
result : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end component;

component lpm_latch0
PORT(gate : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 downto 0);
q : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;

component altaccumulate2
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(15 downto 0);
result : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end component;

component divide4
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
denom : IN STD_LOGIC_VECTOR(15 downto 0);
numer : IN STD_LOGIC_VECTOR(15 downto 0);
quotient : OUT STD_LOGIC_VECTOR(15 downto 0);
remain : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end component;

component altaccumulate0
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 downto 0);
result : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;

component lpm_add_sub1
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(7 downto 0);
datab : IN STD_LOGIC_VECTOR(7 downto 0);
result : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;

component divide0
PORT(clock : IN STD_LOGIC;
aclr : IN STD_LOGIC;
denom : IN STD_LOGIC_VECTOR(7 downto 0);
numer : IN STD_LOGIC_VECTOR(7 downto 0);
quotient : OUT STD_LOGIC_VECTOR(7 downto 0);
remain : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;

signal SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_2 : STD_LOGIC;
signal SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_4 : STD_LOGIC_VECTOR(15 downto 0);
signal SYNTHESIZED_WIRE_5 : STD_LOGIC_VECTOR(15 downto 0);
signal SYNTHESIZED_WIRE_16 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_8 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_17 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_10 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_12 : STD_LOGIC_VECTOR(7 downto 0);
signal SYNTHESIZED_WIRE_14 : STD_LOGIC;
signal SYNTHESIZED_WIRE_15 : STD_LOGIC_VECTOR(7 downto 0);


BEGIN
Del1 <= SYNTHESIZED_WIRE_15;
Del1Y <= SYNTHESIZED_WIRE_3;
kon <= SYNTHESIZED_WIRE_8;
konY <= SYNTHESIZED_WIRE_10;
summa <= SYNTHESIZED_WIRE_5;
Umnozh <= SYNTHESIZED_WIRE_4;
vix <= SYNTHESIZED_WIRE_16;
VixAc <= SYNTHESIZED_WIRE_11;
VixAcY <= SYNTHESIZED_WIRE_12;
vixY <= SYNTHESIZED_WIRE_17;
VuhVuch <= SYNTHESIZED_WIRE_0;
VuhVuchY <= SYNTHESIZED_WIRE_1;



b2v_inst : lpm_ram_dq0
PORT MAP(wren => wren,
clock => Clk1,
address => Adr,
data => x,
q => SYNTHESIZED_WIRE_16);

b2v_inst1 : lpm_mult0
PORT MAP(clock => Clk1,
aclr => RasrUmnozh,
dataa => SYNTHESIZED_WIRE_0,
datab => SYNTHESIZED_WIRE_1,
result => SYNTHESIZED_WIRE_4);

b2v_inst10 : lpm_latch0
PORT MAP(gate => SYNTHESIZED_WIRE_2,
data => SYNTHESIZED_WIRE_3,
q => SYNTHESIZED_WIRE_10);

b2v_inst11 : inhb_0
PORT MAP(2 => Clk1,
3 => Zaver,
1 => SYNTHESIZED_WIRE_2);

b2v_inst2 : altaccumulate2
PORT MAP(clock => Clk1,
aclr => razreshSumm,
data => SYNTHESIZED_WIRE_4,
result => SYNTHESIZED_WIRE_5);

b2v_inst3 : divide4
PORT MAP(clock => Clk1,
aclr => uprdel,
denom => delit,
numer => SYNTHESIZED_WIRE_5,
quotient => cov,
remain => ost);

b2v_inst4 : altaccumulate0
PORT MAP(clock => Clk1,
aclr => Rasr,
data => SYNTHESIZED_WIRE_16,
result => SYNTHESIZED_WIRE_11);

b2v_inst40 : lpm_ram_dq0
PORT MAP(wren => wrenY,
clock => Clk1,
address => AdrY,
data => y,
q => SYNTHESIZED_WIRE_17);

b2v_inst41 : lpm_add_sub1
PORT MAP(clock => Clk1,
aclr => RasrVuch,
dataa => SYNTHESIZED_WIRE_16,
datab => SYNTHESIZED_WIRE_8,
result => SYNTHESIZED_WIRE_0);

b2v_inst42 : lpm_add_sub1
PORT MAP(clock => Clk1,
aclr => RasrVuch,
dataa => SYNTHESIZED_WIRE_17,
datab => SYNTHESIZED_WIRE_10,
result => SYNTHESIZED_WIRE_1);

b2v_inst5 : divide0
PORT MAP(clock => Clk1,
aclr => Zaver,
denom => Const,
numer => SYNTHESIZED_WIRE_11,
quotient => SYNTHESIZED_WIRE_15,
remain => Del2);

b2v_inst6 : divide0
PORT MAP(clock => Clk1,
aclr => Zaver,
denom => Const,
numer => SYNTHESIZED_WIRE_12,
quotient => SYNTHESIZED_WIRE_3,
remain => Del2Y);

b2v_inst7 : altaccumulate0
PORT MAP(clock => Clk1,
aclr => Rasr,
data => SYNTHESIZED_WIRE_17,
result => SYNTHESIZED_WIRE_12);

b2v_inst8 : lpm_latch0
PORT MAP(gate => SYNTHESIZED_WIRE_14,
data => SYNTHESIZED_WIRE_15,
q => SYNTHESIZED_WIRE_8);

b2v_inst9 : inhb_1
PORT MAP(2 => Clk1,
3 => Zaver,
1 => SYNTHESIZED_WIRE_14);

END;
-----

Подскажите пожалуйста как исправить ?
Ответьте тут или на мыло - KPOCCOBOK@yandex.ru Заранее спасибо!