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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ap6 is
port (signal ior,coz:in std_logic;
signal d_in: inout std_logic_vector(7 downto 0);
signal d_out: inout std_logic_vector(7 downto 0));
end ap6;
architecture behav1 of ap6 is
signal n_state: std_logic_vector(7 downto 0);
signal p_state: std_logic_vector(7 downto 0);
begin
d_out <= n_state when (coz = '0' and ior = '1')
else "ZZZZZZZZ";
d_in <= p_state when (coz = '0' and ior = '0')
else "ZZZZZZZZ";
n_state <= d_in;
p_state <= d_out;
end behav1;
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