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-- DESCRIPTION : Component was generated by Alatek IP CORE Generator
-- Details:
-- BCD to seven segments converter
-- segment encoding
-- a
-- +---+
-- f | | b
-- +---+ <- g
-- e | | c
-- +---+
-- d
-- Output enable (EN) active : high
-- Outputs (O) active : low
-- CREATED : 2002-9-19,21 : 19 : 14
-- VERSION : 2.0
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity conv is
port (
I : in std_logic_vector (3 downto 0);
EN : in std_logic;
O : out std_logic_vector (6 downto 0)
);
end entity;
architecture conv_arch of conv is
begin
process(I, EN)
begin
O <= (others => '1');
if EN='1' then
case I is
when "0000" => O <= "1000000"; -- 0
when "0001" => O <= "1111001"; -- 1
when "0010" => O <= "0100100"; -- 2
when "0011" => O <= "0110000"; -- 3
when "0100" => O <= "0011001"; -- 4
when "0101" => O <= "0010010"; -- 5
when "0110" => O <= "0000011"; -- 6
when "0111" => O <= "1111000"; -- 7
when "1000" => O <= "0000000"; -- 8
when "1001" => O <= "0011000"; -- 9
when "1010" => O <= "0000110"; -- E(rror)
when "1011" => O <= "0000110"; -- E(rror)
when "1100" => O <= "0000110"; -- E(rror)
when "1101" => O <= "0000110"; -- E(rror)
when "1110" => O <= "0000110"; -- E(rror)
when "1111" => O <= "1111111"; -- NULL
when others => NULL;
end case;
end if;
end process;
end architecture;
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