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I'm sorry, don't have Russian support.
Anybody knows:
How to create programmable delay for output signal for Virtex (Xilinx)in range of 1 - 20 ns?
I expect the three ways:
1. To write own component with a chain of buffers or latches (latch has more propagation delay) with programmable numbers. I do it.
2. To use programmable delay element in IOB, just how is it?
3. Maybe is there some ready library function?
Second question:
How to justify the edges of output synchronous signals using the constraints in synthesis or place&route tools?
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info@telesys.ru
