Отправлено Engineer 02 января 2003 г. 17:01

Xilinx XC9500-XL временной отчет (часть):
...
Path information for path number 24:
- Setup time: 0.000
= Required time: 10.000

- Propagation time: 0.000
- User constraint on starting point: 10.000
= Slack (critical) : 0.000

Starting point: DATA[15:0] / DATA[0]
Ending point: ret_reg[0] / D
The start point is clocked by clk_25 [rising]
The end point is clocked by clk_25 [rising] on pin C

Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
-------------------------------------------------------------------------
DATA[15:0] Port DATA[0] In 0.000 10.000
DATA[0] Net 2
DATA_ibuf[0] IBUF I In 10.000
DATA_ibuf[0] IBUF O Out 0.000 10.000
DATA_in[0] Net 3
ret_reg[0] FDCE D In 10.000
=========================================================================

Path information for path number 25:
- Setup time: 0.000
= Required time: 10.000

- Propagation time: 0.000
- User constraint on starting point: 10.000
= Slack (critical) : 0.000

Starting point: DATA[15:0] / DATA[1]
Ending point: ret_reg[1] / D
The start point is clocked by clk_25 [rising]
The end point is clocked by clk_25 [rising] on pin C

Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
-------------------------------------------------------------------------
DATA[15:0] Port DATA[1] In 0.000 10.000
DATA[1] Net 2
DATA_ibuf[1] IBUF I In 10.000
DATA_ibuf[1] IBUF O Out 0.000 10.000
DATA_in[1] Net 3
ret_reg[1] FDCE D In 10.000
=========================================================================

##### END TIMING REPORT #####

---------------------------------------
Resource Usage Report for bl_main

Mapping to part: xc95144xltq100-5
Simple gate primitives:
AND2 240 uses
AND2B1 7 uses
FDCE 85 uses
FDPE 3 uses
GND 1 use
OR2 164 uses
XOR2 26 uses

I/O primitives:
IBUF 38 uses
OBUF 25 uses
OBUFT 32 uses

BUFG 2 uses

I/O Register bits: 0
Register bits not including I/Os: 88

Mapper successful!
Process took 2.864 seconds realtime, 2.864 seconds cputime

ТОТ ЖЕ ДИЗАЙН, НО ИСПОЛЬЗУЯ VIRTEX:

Path information for path number 25:
- Setup time: 0.450
= Required time: 9.550

- Propagation time: 10.928
- User constraint on starting point: 10.000
= Slack (non-critical) : -11.378

Starting point: my_cs_n / my_cs_n
Ending point: state_rep11_i[2] / D
The start point is clocked by clk [rising]
The end point is clocked by clk [rising] on pin C

Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
----------------------------------------------------------------------------------
my_cs_n Port my_cs_n In 0.000 10.000
my_cs_n Net 1
my_cs_n_ibuf IBUF I In 10.000
my_cs_n_ibuf IBUF O Out 2.383 12.383
my_cs_n_c Net 7
G_495 LUT4 I3 In 12.383
G_495 LUT4 O Out 1.979 14.363
G_495 Net 8
state_51_1_iv_0_i_2_635 LUT4 I1 In 14.363
state_51_1_iv_0_i_2_635 LUT4 O Out 1.392 15.755
state_51_1_iv_0_i_2_635 Net 1
state_51_1_iv_0_i_2_636 LUT4 I0 In 15.755
state_51_1_iv_0_i_2_636 LUT4 O Out 1.392 17.147
state_51_1_iv_0_i_2_636 Net 1
state_51_1_iv_0_i[2] LUT4 I0 In 17.147
state_51_1_iv_0_i[2] LUT4 O Out 1.802 18.949
state_51_1_iv_0_i[2] Net 6
N_510_i INV I In 18.949
N_510_i INV O Out 1.979 20.928
N_510_i Net 8
state_rep11_i[2] FDPE D In 20.928
==================================================================================

##### END TIMING REPORT #####

---------------------------------------
Resource Usage Report for bl_main

Mapping to part: xcv50bg256-5
Cell usage:
FDCE 32 uses
FDE 65 uses
FDPE 21 uses
GND 1 use
MUXCY 1 use
MUXCY_L 22 uses
MUXF5 1 use
VCC 1 use
XORCY 15 uses

I/O primitives:
IBUF 6 uses
IOBUF 16 uses
IOBUF_F_24 16 uses
OBUF 9 uses
OBUF_F_24 16 uses

BUFGP 2 uses

I/O Register bits: 0
Register bits not including I/Os: 118 (7%)

Global Clock Buffers: 2 of 4 (50%)

Mapping Summary:
Total LUTs: 250 (16%)

Mapper successful!
Process took 6.159 seconds realtime, 6.158 seconds cputime