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architecture BEHAVE of MYMEM is
signal logic0, logic1: std_logic;
component RAMB4_S8
generic( INIT_00, …,INIT_0f : BIT_VECTOR(255 downto 0)
:= X”00….00”);
port (WE, EN, RST, CLK: in STD_LOGIC;
ADDR: in STD_LOGIC_VECTOR(8 downto 0);
DI: in STD_LOGIC_VECTOR(7 downto 0);
DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
begin
logic0 <='0'; logic1 <='1';
ram0: RAMB4_S8
generic map (INIT_00 =>X”0123….CDEF”,
INIT_01 =>X”FEDC…3210”)
port map (WE=>WE, EN=>logic1,
RST=>logic0,
CLK=>CLK,ADDR=>ADDR,
DI=>DIN, DO=>DOUT);
end BEHAVE;
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