Отправлено andrew_b 13 февраля 2003 г. 09:12 В ответ на: Ответ: а что, названия компонентов библиотеки simprims не соответствую оным, перечисляемым library manager? отправлено jm 12 февраля 2003 г. 18:27

library IEEE;
use IEEE.std_logic_1164.all;

-- synthesis translate_off
-- for simulation only not for synthesis!!!
library Simprim;
use Simprim.VComponents.all;
-- synthesis translate_on

entity Timing is
port(
nReset : in std_logic;
Clk : in std_logic;

Reset : out std_logic;
Clk1x : out std_logic;
Clk2x : out std_logic
);
-- define atributes for synthesis using Symplify
attribute syn_black_box : boolean;
end Timing;

architecture arTiming of Timing is

component CLKDLL
port(
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
);
end component;
attribute syn_black_box of CLKDLL : component is true;

component IBUFG
port(
I : in std_logic;
O : out std_logic
);
end component;
attribute syn_black_box of IBUFG : component is true;

component BUFG
port(
I : in std_logic;
O : out std_logic
);
end component;
attribute syn_black_box of BUFG : component is true;

-- synthesis translate_off
-- for simulation only not for synthesis
for mapDLL: CLKDLL use
entity Simprim.X_CLKDLL(X_CLKDLL_V)
generic map(
tipd_CLKIN => (0.000 ns, 0.000 ns)
);

for mapIBUFG: IBUFG use
entity Simprim.X_CKBUF(X_CKBUF_V);

for all: BUFG use
entity Simprim.X_CKBUF(X_CKBUF_V);
-- synthesis translate_on

signal ResetDLL : std_logic;
signal Clk_buf, iClk1x, iClk2x : std_logic;
signal Clk0_dll, Clk2x_dll : std_logic;
signal Locked : std_logic;

begin

mapIBUFG: IBUFG
port map(
I => Clk,
O => Clk_buf
);

ResetDLL <= not nReset;

-- Virtex DLL
mapDLL: CLKDLL
port map(
CLKIN => Clk_buf,
CLKFB => iClk1x,
RST => ResetDLL,
CLK0 => Clk0_dll,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => Clk2x_dll,
CLKDV => open,
LOCKED => Locked
);

mapBUFG: BUFG
port map(
I => Clk0_dll,
O => iClk1x
);

mapBUFG2x: BUFG
port map(
I => Clk2x_dll,
O => iClk2x
);

Reset <= nReset nand Locked;

Clk1x <= iClk1x;
Clk2x <= iClk2x;

end arTiming;