|
|
Project Information c:\max2work\workaltera\test1\test.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/03/2003 10:38:53
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
test EP1K10TC144-1 16 1 0 0 0 % 9 1 %
User Pins: 16 1 0
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
***** Logic for device 'test' compiled without errors.
Device: EP1K10TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S V S S S S S S S S S S S S S
E E E E E E E E E V E E E E E C E E E E E E E V E E E E E E
R R R R R R R R R C R R R R R C i i R R R R R R R C R R R R R R
V V V V V G V V V V C V V V V G V I n i n G V V V V V V V C V V V V V V
E E E E E N E E E E I E E E E N E N 1 n 1 N E E E E E E E I E E E E E E
D D D D D D D D D D O D D D D D D T 4 1 2 D D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | N.C.
N.C. | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | N.C.
RESERVED | 9 100 | RESERVED
N.C. | 10 99 | N.C.
RESERVED | 11 98 | RESERVED
N.C. | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
in2 | 17 92 | in10
in5 | 18 91 | in6
in11 | 19 EP1K10TC144-1 90 | in8
N.C. | 20 89 | N.C.
out | 21 88 | in9
N.C. | 22 87 | in7
in0 | 23 86 | in4
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | N.C.
N.C. | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
N.C. | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R V R G V i i i G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E C E N C n n n N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S C S D C 1 3 1 D D S S C S S S S D S S S S C S
E E E E E E E I E E E E I E _ 5 3 _ E E I E E E E E E E E I E
R R R R R R R O R R R R N R C C R R O R R R R R R R R O R
V V V V V V V V V V V T V K K V V V V V V V V V V V
E E E E E E E E E E E E L L E E E E E E E E E E E
D D D D D D D D D D D D K K D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/22( 77%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 11/86 ( 12%)
Total logic cells used: 9/576 ( 1%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 4.00/4 (100%)
Total fan-in: 36/2304 ( 1%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 1
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 9
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 5
Total number of cascade chains: 1
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 3/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 9/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 9/0
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - B -- INPUT ^ 0 0 0 2 in0
125 - - - -- INPUT ^ 0 0 0 2 in1
17 - - B -- INPUT ^ 0 0 0 2 in2
55 - - - -- INPUT ^ 0 0 0 2 in3
86 - - B -- INPUT ^ 0 0 0 2 in4
18 - - B -- INPUT ^ 0 0 0 2 in5
91 - - B -- INPUT ^ 0 0 0 2 in6
87 - - B -- INPUT ^ 0 0 0 2 in7
90 - - B -- INPUT ^ 0 0 0 2 in8
88 - - B -- INPUT ^ 0 0 0 2 in9
92 - - B -- INPUT ^ 0 0 0 2 in10
19 - - B -- INPUT ^ 0 0 0 2 in11
124 - - - -- INPUT ^ 0 0 0 2 in12
56 - - - -- INPUT ^ 0 0 0 2 in13
126 - - - -- INPUT ^ 0 0 0 2 in14
54 - - - -- INPUT ^ 0 0 0 2 in15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 out
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 24 OR2 ! 4 0 0 1 aout0
- 7 - B 24 OR2 ! 4 0 0 1 aout1
- 8 - B 24 OR2 ! 4 0 0 1 aout2
- 1 - B 22 OR2 ! 4 0 0 1 aout3
- 1 - B 24 OR2 4 0 0 1 :144
- 2 - B 24 OR2 s ! 4 1 0 1 ~179~1
- 3 - B 24 OR2 s ! 4 1 0 1 ~179~2
- 4 - B 24 OR2 s ! 4 1 0 1 ~179~3
- 5 - B 24 OR2 0 5 1 0 :179
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 10/ 96( 10%) 0/ 48( 0%) 2/ 48( 4%) 10/16( 62%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
§
Device-Specific Information: c:\max2work\workaltera\test1\test.rpt
test
** EQUATIONS **
in0 : INPUT;
in1 : INPUT;
in2 : INPUT;
in3 : INPUT;
in4 : INPUT;
in5 : INPUT;
in6 : INPUT;
in7 : INPUT;
in8 : INPUT;
in9 : INPUT;
in10 : INPUT;
in11 : INPUT;
in12 : INPUT;
in13 : INPUT;
in14 : INPUT;
in15 : INPUT;
-- Node name is 'aout0' from file "test.tdf" line 12, column 30
-- Equation name is 'aout0', location is LC6_B24, type is buried.
!aout0 = aout0~NOT;
aout0~NOT = LCELL( _EQ001);
_EQ001 = in1 & in3
# in0 & in1
# in0 & in3
# in1 & in2
# in2 & in3
# in0 & in2
# !in0 & !in1 & !in2 & !in3;
-- Node name is 'aout1' from file "test.tdf" line 18, column 30
-- Equation name is 'aout1', location is LC7_B24, type is buried.
!aout1 = aout1~NOT;
aout1~NOT = LCELL( _EQ002);
_EQ002 = in5 & in7
# in4 & in5
# in4 & in7
# in5 & in6
# in6 & in7
# in4 & in6
# !in4 & !in5 & !in6 & !in7;
-- Node name is 'aout2' from file "test.tdf" line 24, column 31
-- Equation name is 'aout2', location is LC8_B24, type is buried.
!aout2 = aout2~NOT;
aout2~NOT = LCELL( _EQ003);
_EQ003 = in9 & in11
# in8 & in9
# in8 & in11
# in9 & in10
# in10 & in11
# in8 & in10
# !in8 & !in9 & !in10 & !in11;
-- Node name is 'aout3' from file "test.tdf" line 30, column 32
-- Equation name is 'aout3', location is LC1_B22, type is buried.
!aout3 = aout3~NOT;
aout3~NOT = LCELL( _EQ004);
_EQ004 = in13 & in15
# in12 & in13
# in12 & in15
# in13 & in14
# in14 & in15
# in12 & in14
# !in12 & !in13 & !in14 & !in15;
-- Node name is 'out' from file "test.tdf" line 33, column 2
-- Equation name is 'out', type is output
out = !_LC5_B24;
-- Node name is ':144' from file "test.tdf" line 34, column 22
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ005C);
_EQ005C = _EQ005;
_EQ005 = !in0 & !in1 & !in2
# !in0 & !in2 & !in3
# !in1 & !in2 & !in3
# !in0 & !in1 & !in3;
-- Node name is '~179~1' from file "test.tdf" line 39, column 4
-- Equation name is '~179~1', location is LC2_B24, type is buried.
-- synthesized logic cell
!_LC2_B24 = _LC2_B24~NOT;
_LC2_B24~NOT = LCELL( _EQ006C);
_EQ006C = _EQ006 & CASCADE( _EQ005C);
_EQ006 = !in4 & !in5 & !in6
# !in4 & !in6 & !in7
# !in5 & !in6 & !in7
# !in4 & !in5 & !in7;
-- Node name is '~179~2' from file "test.tdf" line 39, column 4
-- Equation name is '~179~2', location is LC3_B24, type is buried.
-- synthesized logic cell
!_LC3_B24 = _LC3_B24~NOT;
_LC3_B24~NOT = LCELL( _EQ007C);
_EQ007C = _EQ007 & CASCADE( _EQ006C);
_EQ007 = !in8 & !in9 & !in10
# !in8 & !in10 & !in11
# !in9 & !in10 & !in11
# !in8 & !in9 & !in11;
-- Node name is '~179~3' from file "test.tdf" line 39, column 4
-- Equation name is '~179~3', location is LC4_B24, type is buried.
-- synthesized logic cell
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = LCELL( _EQ008C);
_EQ008C = _EQ008 & CASCADE( _EQ007C);
_EQ008 = !in12 & !in13 & !in14
# !in12 & !in14 & !in15
# !in13 & !in14 & !in15
# !in12 & !in13 & !in15;
-- Node name is ':179' from file "test.tdf" line 39, column 4
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ009C);
_EQ009C = _EQ009 & CASCADE( _EQ008C);
_EQ009 = !aout0 & !aout1 & !aout3
# !aout0 & !aout1 & !aout2
# !aout0 & !aout2 & !aout3
# !aout1 & !aout2 & !aout3;
§
Project Information c:\max2work\workaltera\test1\test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = FAST
Logic option settings in 'FAST' style for 'ACEX1K' family
CARRY_CHAIN = auto
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = auto
CASCADE_CHAIN_LENGTH = 5
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = on
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 10
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
E-mail: 
info@telesys.ru
