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module Shift_reg_v1 (clk, d, q);
parameter w = 2000;
input clk, d;
output [w-1:0] q;
reg [w-1:0] q, qq;
integer i;
always @(posedge clk)
begin
for ( i = 1; i < w; i = i + 1 ) qq[i] = q[i-1];
qq[0] = d;
end
always @(negedge clk)
q[w-1:0] = qq[w-1:0];
endmodule
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