Ответ: Только нафиг нужен Viterbi ?? Туфта .. ищите Turbo MAP вот это алгоритм, а за RS я вообще молчу. («Телесистемы»: Конференция «Программируемые логические схемы и их применение»)

[an error occurred while processing this directive] Ответ: Только нафиг нужен Viterbi ?? Туфта .. ищите Turbo MAP вот это алгоритм, а за RS я вообще молчу.

(«Телесистемы»: Конференция «Программируемые логические схемы и их применение»)

Отправлено Jackal 23 марта 2003 г. 12:02
В ответ на: Рализация на ПЛИС алгоритмов помехоустойчивого кодирования - декодирования? отправлено SKov 19 марта 2003 г. 12:31

ENTITY viterbi_encoder IS
PORT( xin : IN BIT;
clk : IN BIT;
reset_n : IN BIT;
vdd : IN BIT;
vss : IN BIT;
y : OUT BIT_VECTOR(1 DOWNTO 0)
);
END viterbi_encoder;

ARCHITECTURE data_flow OF viterbi_encoder IS
SIGNAL d : BIT_VECTOR (1 DOWNTO 0);
SIGNAL y1_1 : BIT;

COMPONENT dff
PORT( din : IN BIT;
clk : IN BIT;
reset_n : IN BIT;
vdd : IN BIT;
vss : IN BIT;
dout : OUT BIT
);
END COMPONENT;
COMPONENT xr2_y
PORT( i0,i1 : IN BIT;
t : OUT BIT;
vdd : IN BIT;
vss : IN BIT
);
END COMPONENT;

BEGIN
d1 : dff PORT MAP(xin,clk,reset_n,vdd,vss,d(0));
d2 : dff PORT MAP(d(0),clk,reset_n,vdd,vss,d(1));
y_1 : xr2_y PORT MAP (d(0), d(1), y(0),vdd,vss);
y1_0: xr2_y PORT MAP (xin, d(0), y1_1,vdd,vss);
y1 : xr2_y PORT MAP (y1_1, d(1), y(1),vdd,vss);
END data_flow;
---------------------------------------------------------------------
ENTITY viterbi is
port (
Y_in_0 : in BIT;
Y_in_1 : in bit;
clk, reset_n : in bit;
vdd : in bit;
vss : in bit;
decode_out : out bit_vector (1 downto 0));
end viterbi;

architecture struktur of viterbi is

COMPONENT viterbi_distances
port(
Y_in_0 : in BIT;
Y_in_1 : in bit;
vdd : in bit;
vss : in BIT;
in0, in1, in2, in3 : out bit_vector (1 downto 0)
);
END COMPONENT;
COMPONENT compute_metric
port (m_out0, m_out1, m_out2, m_out3 : in bit_vector(3 downto 0);
s0, s1, s2, s3 : in bit_vector(1 downto 0);
vdd,vss : in bit;
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : out bit_vector(3 downto 0));
END COMPONENT;
COMPONENT metric
port(
m_in0, m_in1, m_in2, m_in3 : in bit_vector(3 downto 0);
clk : IN BIT;
reset_n : in BIT;
vdd : IN BIT;
vss : IN BIT;
m_out0,m_out1,m_out2,m_out3 : out bit_vector(3 downto 0)
);
END COMPONENT;
COMPONENT acs_enable
port(
clk : IN BIT;
reset_n : in BIT;
vdd : IN BIT;
vss : IN BIT;
res_3 : out BIT);
end COMPONENT;
COMPONENT compare_metric
PORT(
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : IN BIT_VECTOR(3 DOWNTO 0);
vdd,vss : IN BIT;
b,s,e : OUT BIT_vector(3 downto 0)
);
END COMPONENT;
COMPONENT select_metric
port(
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : in bit_vector(3 downto 0);
rst_3 : in bit;
b,s,e : IN BIT_vector(3 downto 0);
vdd,vss : IN BIT;
out0, out1, out2, out3 : out bit_vector(3 downto 0);
acs : out bit_vector(3 downto 0)
);
end COMPONENT;
COMPONENT compare
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
b0 : OUT BIT_VECTOR(2 DOWNTO 0);
s0 : OUT BIT_VECTOR(2 DOWNTO 0);
e0 : OUT BIT_VECTOR(2 DOWNTO 0);
b1 : OUT BIT_VECTOR(1 DOWNTO 0);
s1 : OUT BIT_VECTOR(1 DOWNTO 0);
e1 : OUT BIT_VECTOR(1 DOWNTO 0);
b2 : OUT BIT;
s2 : OUT BIT;
e2 : OUT BIT
);
END COMPONENT;
COMPONENT find_smallest
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
b0 : IN BIT_VECTOR(2 DOWNTO 0);
s0 : IN BIT_VECTOR(2 DOWNTO 0);
e0 : IN BIT_VECTOR(2 DOWNTO 0);
b1 : IN BIT_VECTOR(1 DOWNTO 0);
s1 : IN BIT_VECTOR(1 DOWNTO 0);
e1 : IN BIT_VECTOR(1 DOWNTO 0);
b2 : IN BIT;
s2 : IN BIT;
e2 : IN BIT;
vdd : IN BIT;
vss : IN BIT;
control : OUT BIT_VECTOR(1 DOWNTO 0);
smallest: out bit_vector (3 downto 0)
);
END COMPONENT;
COMPONENT reduce
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
smallest: IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
m_in0,m_in1,m_in2,m_in3: out bit_vector (3 downto 0)
);
END COMPONENT;
COMPONENT path_memory
port(
acs : in bit_vector(3 downto 0);
control : in bit_vector(1 downto 0);
clk : in bit;
reset_n : in bit;
vdd : in bit;
vss : in bit;
decode_out : out bit_vector(1 downto 0)
);
END COMPONENT;

SIGNAL in0, in1, in2, in3 : bit_vector (1 downto 0);
signal m_in0,m_in1,m_in2,m_in3 : bit_vector (3 downto 0);
signal m_out0,m_out1,m_out2,m_out3 : bit_vector (3 downto 0);
signal out0,out1,out2,out3 : bit_vector (3 downto 0);
signal p0_0,p1_0,p2_1,p3_1 : bit_vector (3 downto 0);
signal p0_2,p1_2,p2_3,p3_3 : bit_vector (3 downto 0);
signal b,s,e : bit_vector (3 downto 0);
signal b0,s0,e0 : bit_vector (2 downto 0);
signal b1,s1,e1 : bit_vector (1 downto 0);
signal b2,s2,e2 : bit;
signal acs : bit_vector (3 downto 0);
signal control : bit_vector (1 downto 0);
signal smallest : bit_vector (3 downto 0);
signal res_3 : bit;

begin
u0: viterbi_distances port map(Y_in_0,Y_in_1,vdd,vss,in0,in1,in2,in3);
u1: compute_metric port map (m_out0,m_out1,m_out2,m_out3,in0,in1,in2,in3,vdd,vss,p0_0,p1_0,p2_1,p3_1,p0_2,p1_2,p2_3,p3_3);
u2: metric port map (m_in0,m_in1,m_in2,m_in3,clk,reset_n,vdd,vss,m_out0,m_out1,m_out2,m_out3);
u3: acs_enable port map (clk,reset_n,vdd,vss,res_3);
u4: compare_metric port map (p0_0,p1_0,p2_1,p3_1,p0_2,p1_2,p2_3,p3_3,vdd,vss,b,s,e);
u5: select_metric port map (p0_0,p1_0,p2_1,p3_1,p0_2,p1_2,p2_3,p3_3,res_3,b,s,e,vdd,vss,out0,out1,out2,out3);
u6: compare port map (out0,out1,out2,out3,vdd,vss,b0,s0,e0,b1,s1,e1,b2,s2,e2);
u7: find_smallest port map (out0,out1,out2,out3,b0,s0,e0,b1,s1,e1,b2,s2,e2,vdd,vss,control,smallest);
u8: reduce port map (out0,out1,out2,out3,smallest,vdd,vss,m_in0,m_in1,m_in2,m_in3);
u9: path_memory port map (acs, control,clk, reset_n,vdd,vss, decode_out);
end struktur;
---------------------------------------------------------------------
ENTITY viterbi_distances IS
port(
Y_in_0 : in BIT;
Y_in_1 : in bit;
vdd,vss : in bit;
in0, in1, in2, in3 : out bit_vector (1 downto 0)
);
END viterbi_distances;

ARCHITECTURE data_flow of viterbi_distances is
signal temp : bit_vector (7 downto 0);

begin
WITH (Y_in_1 & Y_in_0) SELECT
temp <= "00010110" WHEN "00",
"01001001" WHEN "01",
"01100001" WHEN "10",
"10010100" WHEN "11";

in0 <= temp(7 downto 6);
in1 <= temp(5 downto 4);
in2 <= temp(3 downto 2);
in3 <= temp(1 downto 0);

end data_flow;
---------------------------------------------------------------------
ENTITY compute_metric IS
port (m_out0, m_out1, m_out2, m_out3 : in bit_vector(3 downto 0);
s0, s1, s2, s3 : in bit_vector(1 downto 0);
vdd,vss : in bit;
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : out bit_vector(3 downto 0));
END compute_metric;

ARCHITECTURE struktur OF compute_metric IS
COMPONENT full_adder
PORT (
a: IN BIT;
b: IN BIT;
cin: IN BIT;
vdd: IN BIT;
vss: IN BIT;
sum: OUT BIT;
cout: OUT BIT
);
END COMPONENT;
signal c0_0, c0_1, c0_2 : BIT;
signal c1_0, c1_1, c1_2 : BIT;
signal c2_0, c2_1, c2_2 : BIT;
signal c3_0, c3_1, c3_2 : BIT;
signal c4_0, c4_1, c4_2 : BIT;
signal c5_0, c5_1, c5_2 : BIT;
signal c6_0, c6_1, c6_2 : BIT;
signal c7_0, c7_1, c7_2 : BIT;

BEGIN
full0_0 : full_adder port map (m_out0(0),s0(0),vss,vdd,vss,p0_0(0),c0_0);
full1_0 : full_adder port map (m_out0(1),s0(1),c0_0,vdd,vss,p0_0(1),c0_1);
full2_0 : full_adder port map (m_out0(2),vss,c0_1,vdd,vss,p0_0(2),c0_2);
full3_0 : full_adder port map (m_out0(3),vss,c0_2,vdd,vss,p0_0(3));

full0_1 : full_adder port map (m_out0(0),s3(0),vss,vdd,vss,p0_2(0),c1_0);
full1_1 : full_adder port map (m_out0(1),s3(1),c1_0,vdd,vss,p0_2(1),c1_1);
full2_1 : full_adder port map (m_out0(2),vss,c1_1,vdd,vss,p0_2(2),c1_2);
full3_1 : full_adder port map (m_out0(3),vss,c1_2,vdd,vss,p0_2(3));

full0_2 : full_adder port map (m_out2(0),s1(0),vss,vdd,vss,p2_3(0),c2_0);
full1_2 : full_adder port map (m_out2(1),s1(1),c2_0,vdd,vss,p2_3(1),c2_1);
full2_2 : full_adder port map (m_out2(2),vss,c2_1,vdd,vss,p2_3(2),c2_2);
full3_2 : full_adder port map (m_out2(3),vss,c2_2,vdd,vss,p2_3(3));

full0_3 : full_adder port map (m_out2(0),s2(0),vss,vdd,vss,p2_1(0),c3_0);
full1_3 : full_adder port map (m_out2(1),s2(1),c3_0,vdd,vss,p2_1(1),c3_1);
full2_3 : full_adder port map (m_out2(2),vss,c3_1,vdd,vss,p2_1(2),c3_2);
full3_3 : full_adder port map (m_out2(3),vss,c3_2,vdd,vss,p2_1(3));

full0_4 : full_adder port map (m_out1(0),s3(0),vss,vdd,vss,p1_0(0),c4_0);
full1_4 : full_adder port map (m_out1(1),s3(1),c4_0,vdd,vss,p1_0(1),c4_1);
full2_4 : full_adder port map (m_out1(2),vss,c4_1,vdd,vss,p1_0(2),c4_2);
full3_4 : full_adder port map (m_out1(3),vss,c4_2,vdd,vss,p1_0(3));

full0_5 : full_adder port map (m_out1(0),s0(0),vss,vdd,vss,p1_2(0),c5_0);
full1_5 : full_adder port map (m_out1(1),s0(1),c5_0,vdd,vss,p1_2(1),c5_1);
full2_5 : full_adder port map (m_out1(2),vss,c5_1,vdd,vss,p1_2(2),c5_2);
full3_5 : full_adder port map (m_out1(3),vss,c5_2,vdd,vss,p1_2(3));

full0_6 : full_adder port map (m_out3(0),s1(0),vss,vdd,vss,p3_1(0),c6_0);
full1_6 : full_adder port map (m_out3(1),s1(1),c6_0,vdd,vss,p3_1(1),c6_1);
full2_6 : full_adder port map (m_out3(2),vss,c6_1,vdd,vss,p3_1(2),c6_2);
full3_6 : full_adder port map (m_out3(3),vss,c6_2,vdd,vss,p3_1(3));

full0_7 : full_adder port map (m_out3(0),s2(0),vss,vdd,vss,p3_3(0),c7_0);
full1_7 : full_adder port map (m_out3(1),s2(1),c7_0,vdd,vss,p3_3(1),c7_1);
full2_7 : full_adder port map (m_out3(2),vss,c7_1,vdd,vss,p3_3(2),c7_2);
full3_7 : full_adder port map (m_out3(3),vss,c7_2,vdd,vss,p3_3(3));
END struktur;
---------------------------------------------------------------------
ENTITY compare_metric IS
PORT(
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : IN BIT_VECTOR(3 DOWNTO 0);
vdd,vss : IN BIT;
b,s,e : OUT BIT_vector(3 downto 0)
);
END compare_metric;

ARCHITECTURE struktur OF compare_metric IS

COMPONENT comparator4
PORT ( a : IN BIT_VECTOR(3 DOWNTO 0);
b : IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
a_bigger : OUT BIT;
a_smaller: OUT BIT;
equal : OUT BIT
);
END COMPONENT;

BEGIN
compare0 : comparator4 port map (p0_0,p1_0,vdd,vss,b(0),s(0),e(0));
compare1 : comparator4 port map (p2_1,p3_1,vdd,vss,b(1),s(1),e(1));
compare2 : comparator4 port map (p0_2,p1_2,vdd,vss,b(2),s(2),e(2));
compare3 : comparator4 port map (p2_3,p3_3,vdd,vss,b(3),s(3),e(3));
END struktur;

ENTITY select_metric is
port(
p0_0, p1_0, p2_1, p3_1, p0_2, p1_2, p2_3, p3_3 : in bit_vector(3 downto 0);
rst_3 : in bit;
b,s,e : IN BIT_vector(3 downto 0);
vdd,vss : IN BIT;
out0, out1, out2, out3 : out bit_vector(3 downto 0);
acs : out bit_vector(3 downto 0)
);
end select_metric;

ARCHITECTURE data_flow OF select_metric IS

BEGIN
out0 <= p0_0 when (s(0) or e(0))='1' else p1_0;
out1 <= p2_1 when (s(1) or e(1))='1' else p3_1;
out2 <= p0_2 when (s(2) or e(2))='1' else p1_2;
out3 <= p2_3 when (s(3) or e(3))='1' else p3_3;
acs(0) <= '0' when (s(0) or e(0))='1' else '1';
acs(1) <= '0' when (s(1) or e(1))='1' else '1';
acs(2) <= '0' when (s(2) or e(2))='1' else '1';
acs(3) <= '0' when (s(3) or e(3))='1' else '1';
END data_flow;
---------------------------------------------------------------------
ENTITY compare IS
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
b0 : OUT BIT_VECTOR(2 DOWNTO 0);
s0 : OUT BIT_VECTOR(2 DOWNTO 0);
e0 : OUT BIT_VECTOR(2 DOWNTO 0);
b1 : OUT BIT_VECTOR(1 DOWNTO 0);
s1 : OUT BIT_VECTOR(1 DOWNTO 0);
e1 : OUT BIT_VECTOR(1 DOWNTO 0);
b2 : OUT BIT;
s2 : OUT BIT;
e2 : OUT BIT
);
END compare;

ARCHITECTURE struktur OF compare IS

COMPONENT comparator4
PORT ( a : IN BIT_VECTOR(3 DOWNTO 0);
b : IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
a_bigger : OUT BIT;
a_smaller: OUT BIT;
equal : OUT BIT
);
END COMPONENT;

BEGIN
compare0_1 : comparator4 port map (input0,input1,vdd,vss,b0(0),s0(0),e0(0));
compare0_2 : comparator4 port map (input0,input2,vdd,vss,b0(1),s0(1),e0(1));
compare0_3 : comparator4 port map (input0,input3,vdd,vss,b0(2),s0(2),e0(2));
compare1_2 : comparator4 port map (input1,input2,vdd,vss,b1(0),s1(0),e1(0));
compare1_3 : comparator4 port map (input1,input3,vdd,vss,b1(1),s1(1),e1(1));
compare2_3 : comparator4 port map (input2,input3,vdd,vss,b2,s2,e2);
END struktur;

ENTITY find_smallest is
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
b0 : IN BIT_VECTOR(2 DOWNTO 0);
s0 : IN BIT_VECTOR(2 DOWNTO 0);
e0 : IN BIT_VECTOR(2 DOWNTO 0);
b1 : IN BIT_VECTOR(1 DOWNTO 0);
s1 : IN BIT_VECTOR(1 DOWNTO 0);
e1 : IN BIT_VECTOR(1 DOWNTO 0);
b2 : IN BIT;
s2 : IN BIT;
e2 : IN BIT;
vdd : IN BIT;
vss : IN BIT;
control : OUT BIT_VECTOR(1 DOWNTO 0);
smallest: out bit_vector (3 downto 0)
);
END find_smallest;

architecture data_flow of find_smallest is

signal temp : bit_vector(3 downto 0);

BEGIN
temp <= input0 WHEN ((s0(0) or e0(0)) and (s0(1) or e0(1)) and (s0(2) or e0(2)))='1' else
input1 WHEN (b0(0) and (s1(0) or e1(0)) and (s1(1) or e1(1)))='1' else
input2 WHEN (b0(1) and b1(0) and (s2 or e2))='1' else
input3;

control <= "00" WHEN ((s0(0) or e0(0)) and (s0(1) or e0(1)) and (s0(2) or e0(2))) ='1' else
"01" WHEN (b0(0) and (s1(0) or e1(0)) and (s1(1) or e1(1))) ='1' else
"10" WHEN (b0(1) and b1(0) and (s2 or e2)) ='1' else
"11";
smallest <= temp;
END data_flow;

ENTITY reduce is
PORT(
input0 : IN BIT_VECTOR(3 DOWNTO 0);
input1 : IN BIT_VECTOR(3 DOWNTO 0);
input2 : IN BIT_VECTOR(3 DOWNTO 0);
input3 : IN BIT_VECTOR(3 DOWNTO 0);
smallest: IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
m_in0,m_in1,m_in2,m_in3: out bit_vector (3 downto 0)
);
END reduce;

architecture struktur of reduce is

COMPONENT subtract4
PORT ( a : IN BIT_VECTOR(3 DOWNTO 0);
b : IN BIT_VECTOR(3 DOWNTO 0);
vdd : IN BIT;
vss : IN BIT;
dif : OUT BIT_VECTOR(3 DOWNTO 0)
);
END COMPONENT;

BEGIN
min0: subtract4 port map(input0,smallest,vdd,vss,m_in0);
min1: subtract4 port map(input1,smallest,vdd,vss,m_in1);
min2: subtract4 port map(input2,smallest,vdd,vss,m_in2);
min3: subtract4 port map(input3,smallest,vdd,vss,m_in3);
END struktur;
---------------------------------------------------------------------
ENTITY metric IS
port(
m_in0, m_in1, m_in2, m_in3 : in bit_vector(3 downto 0);
clk : IN BIT;
reset_n : in BIT;
vdd : IN BIT;
vss : IN BIT;
m_out0,m_out1,m_out2,m_out3 : out bit_vector(3 downto 0)
);
END metric;

ARCHITECTURE struktur OF metric IS
component dff
port (
din : in bit;
clk : in bit;
reset_n : in bit;
vdd : in BIT;
vss : IN BIT;
dout : OUT BIT
);
end component;

BEGIN
metric3_0: dff port map(m_in3(0), clk, reset_n,vdd,vss, m_out3(0));
metric3_1: dff port map(m_in3(1), clk, reset_n,vdd,vss, m_out3(1));
metric3_2: dff port map(m_in3(2), clk, reset_n,vdd,vss, m_out3(2));
metric3_3: dff port map(m_in3(3), clk, reset_n,vdd,vss, m_out3(3));

metric2_0: dff port map(m_in2(0), clk, reset_n,vdd,vss, m_out2(0));
metric2_1: dff port map(m_in2(1), clk, reset_n,vdd,vss, m_out2(1));
metric2_2: dff port map(m_in2(2), clk, reset_n,vdd,vss, m_out2(2));
metric2_3: dff port map(m_in2(3), clk, reset_n,vdd,vss, m_out2(3));

metric1_0: dff port map(m_in1(0), clk, reset_n,vdd,vss, m_out1(0));
metric1_1: dff port map(m_in1(1), clk, reset_n,vdd,vss, m_out1(1));
metric1_2: dff port map(m_in1(2), clk, reset_n,vdd,vss, m_out1(2));
metric1_3: dff port map(m_in1(3), clk, reset_n,vdd,vss, m_out1(3));

metric0_0: dff port map(m_in0(0), clk, reset_n,vdd,vss, m_out0(0));
metric0_1: dff port map(m_in0(1), clk, reset_n,vdd,vss, m_out0(1));
metric0_2: dff port map(m_in0(2), clk, reset_n,vdd,vss, m_out0(2));
metric0_3: dff port map(m_in0(3), clk, reset_n,vdd,vss, m_out0(3));
END struktur;
---------------------------------------------------------------------
ENTITY path_memory IS
port(
acs : in bit_vector(3 downto 0);
control : in bit_vector(1 downto 0);
clk : in bit;
reset_n : in bit;
vdd : in bit;
vss : in bit;
decode_out : out bit_vector(1 downto 0)
);
END path_memory;

ARCHITECTURE struktur of path_memory is

component path
port(
path_in : in bit_vector(3 downto 0);
clk : in BIT;
reset_n : in BIT;
vdd : in BIT;
vss : IN BIT;
path_out: out bit_vector(3 downto 0)
);
end component;
component back
port(
state : in BIT_VECTOR (1 downto 0);
survival_data : in BIT_vector (3 downto 0);
vdd : in bit;
vss : in bit;
output : out BIT_vector (1 downto 0)
);
end component;
component dff
port (
din : in bit;
clk : in bit;
reset_n : in bit;
vdd : in bit;
vss : in bit;
dout : out bit
);
end component;

signal out1,out2,out3,out4,out5,out6,out7,
out8,out9,out10,out11 : bit_vector(3 downto 0);
signal state1,state2,state3,state4,state5,
state6,state7,state8,state9,state10,
state11 : bit_vector(1 downto 0);

begin
x1 : path port map(acs, clk, reset_n, vdd, vss, out1);
x2 : path port map(out1, clk, reset_n, vdd, vss, out2);
x3 : path port map(out2, clk, reset_n, vdd, vss, out3);
x4 : path port map(out3, clk, reset_n, vdd, vss, out4);
x5 : path port map(out4, clk, reset_n, vdd, vss, out5);
x6 : path port map(out5, clk, reset_n, vdd, vss, out6);
x7 : path port map(out6, clk, reset_n, vdd, vss, out7);
x8 : path port map(out7, clk, reset_n, vdd, vss, out8);
x9 : path port map(out8, clk, reset_n, vdd, vss, out9);
x10: path port map(out9, clk, reset_n, vdd, vss, out10);
x11: path port map(out10, clk, reset_n, vdd, vss, out11);
b11: back port map(control,out1,vdd,vss, state1);
b10: back port map(state1, out2, vdd,vss,state2);
b9: back port map(state2, out3, vdd,vss,state3);
b8: back port map(state3, out4, vdd,vss,state4);
b7: back port map(state4, out5, vdd,vss,state5);
b6: back port map(state5, out6, vdd,vss,state6);
b5: back port map(state6, out7, vdd,vss,state7);
b4: back port map(state7, out8, vdd,vss,state8);
b3: back port map(state8, out9, vdd,vss,state9);
b2: back port map(state9, out10, vdd,vss,state10);
b1: back port map(state10, out11, vdd,vss,state11);
buff1: dff port map (state11(0), clk,reset_n,vdd,vss, decode_out(0));
buff2: dff port map (state11(1), clk,reset_n,vdd,vss, decode_out(1));
end struktur;

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Спасибо за программу - очень интересно, правда я почти ничего не понял, но — SKov (23.03.2003 19:16, 337 байт)
- Ответ: Что то типа Turb-Log только еще лучше ;)) — Jackal (23.03.2003 22:04, 222 байт)
  - Ну уж это вы загнули ;) Лучше Turb-Log уж точно ничего быть не может! Кстати, а что это такое Turb-Log? — SKov (23.03.2003 23:35, пустое)
    - Ответ: Так сокращают или обзывают ;)) Log-MAP Turbo Codes - Turbo - Log, а Max-Log-MAP Turbo Codes - Turbo MAP — Jackal (24.03.2003 20:58, пустое)
      - Ну так ссылку + — SKov (25.03.2003 07:42, пустое)
        
        Блин, опять промахнулся по клаве.. Ну так ссылку с описанием алгоритма в и-нете или на IEEE IT или еще куда, можно в студию? Или это собственная разработка, не имеющая аналогов в этой жизни ? — SKov (25.03.2003 07:46, пустое)
      - Ну так ссылку + — SKov (25.03.2003 07:42, пустое)

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