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library IEEE;
use IEEE.std_logic_1164.all;
entity SyncEdge is
port (Clk, InPulse: in std_logic;
PEdge : out std_logic;
NEdge : out std_logic;
PEdgeN : out std_logic;
NEdgeN : out std_logic );
end entity SyncEdge;
architecture ArchSyncEdge of SyncEdge is
signal Tmp1, Tmp2 : std_logic;
begin
DetectE: process (Clk) --Sync Edge Detector
begin
if (Clk'event and Clk = '1') then
Tmp1 <= InPulse;
Tmp2 <= Tmp1;
end if;
end process DetectE;
PEdge <= Tmp1 and (not(Tmp2));
PEdgeN <= not(Tmp1 and (not(Tmp2)));
NEdge <= (not(Tmp1) and Tmp2);
NEdgeN <= not(not(Tmp1) and Tmp2);
end ArchSyncEdge;
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