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ПАР выдал ошибку:(((.
ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any Primary / econdary pair of clocks may enter any region. For further information see the "Global clocks" section in the V-II Hand-Book (Chapter 2: Design Considerations)
Что он от меня хочет?
Проект под Xilinx Virtex2
из 16 глобальных клоков использует 14.
часть лигики работает по мультиплексированным клокам. Клоки мультипликсируються через BUFGMUX.
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