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а это из pdf "Handling Libraries in VHDL, Verilog and EDIF"
library for this file.
When the simulator loads the top-level module, it must also load all the modules instantiated
therein and in the underlying hierarchy levels. Verilog itself does not provide mechanisms for
specifying the resource library or libraries from which the hierarchically lower modules are to be
loaded. Instead, Active-HDL searches the default working library and the libraries listed on the
Verilog Libraries tab of the Design Settings dialog box. You can add any attached library to this
list. If a library you want to add is not attached, you must attach it first using Library Manager.
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