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Потаюсь откомпилировать код представленный ниже. Компиляция начинается, доходит без ошибок до «Low Level Synthesis», а дальше тормозит, сколько не ждал она не заканчивается. Не могли бы вы подсказать в чем ошибка.
Заранее благодарю.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- pragma translate_off
library WORK;
use work.MY.all;
library unisim;
use unisim.all;
-- pragma translate_on
entity test_ram is
generic (
datawidth : integer := 12;
adrsdepth : integer := 8
);
port (
RESET : in std_logic;
CLK : in std_logic;
ADR : in std_logic_vector(31 downto 0);
DATA : in std_logic_vector(11 downto 0);
ADo : out std_logic_vector(31 downto 0);
MEM_HIT : in std_logic;
RD : in std_logic;
Write : in std_logic;
ADRESS : in std_logic_vector(9 downto 0);
DRDY : out std_logic
);
end test_ram;
architecture RTL of test_ram is
constant adrssize : integer := 2**adrsdepth;
type ram_type is array (adrssize - 1 downto 0) of std_logic_vector (datawidth - 1 downto 0);
signal RAM : ram_type;
constant Zero_32 : std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
constant Zero_16 : std_logic_vector(15 downto 0):= "0000000000000000";
constant HI_Z_32 : std_logic_vector(31 downto 0):= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
constant HI_Z_12 : std_logic_vector(11 downto 0):= "ZZZZZZZZZZZZ";
constant Zero_20 : std_logic_vector(19 downto 0):= "00000000000000000000";
constant HI_Z_20 : std_logic_vector(19 downto 0):= "ZZZZZZZZZZZZZZZZZZZZ";
signal DO : std_logic_vector(31 downto 0);
signal RD_EN, Mem_area, W,E : std_logic;
begin
Mem_area <= '1' when ADR(22 downto 10)="0000000000000" else '0';
RD_EN <= '1' when RD='1' and MEM_HIT='1' and Mem_area='1' else '0';
process(RESET, CLK)
begin
if RESET='1' then
DRDY <= '0';
elsif (CLK'event and CLK = '1') then
DRDY <= MEM_HIT and Mem_area; -- 1-takt delay for RAM read
if Write = '1' then
RAM(conv_integer(ADRESS(7 downto 0))) <= DATA;
end if;
end if;
end process;
buf_ado : ADo(11 downto 0) <= RAM(conv_integer(ADR(9 downto 2))) when RD_EN='1' else HI_Z_12;
ADo(31 downto 12) <= Zero_20 when RD_EN='1' else HI_Z_20;
end RTL;
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info@telesys.ru
