Отправлено Диман 05 июня 2001 г. 18:18

//WDT
module wdt(CLK, TGL, OUT);
input CLK, TGL;
output OUT; //1 == TimeOut

reg OUT;
reg nReset;
//Rising Edge TGL store
reg regClrRE;
always @(posedge TGL or negedge nReset)
begin
if(!nReset) regClrRE <= 0; //async. reset
else regClrRE <= 1;
end
//Falling Edge TGL store
reg regClrFE;
always @(negedge TGL or negedge nReset)
begin
if(!nReset) regClrFE <= 0;
else regClrFE <= 1;
end
//WDT Counter with Count_Enable and async. reset lines
wire ResetWDT;
assign ResetWDT = regClrRE | regClrFE;
reg [7:0]CntrWDT;
wire EnaCntrWDT;
assign EnaCntrWDT = CntrWDT != 255;
always @(posedge CLK or posedge ResetWDT)
begin
if(ResetWDT) CntrWDT <= 0;//async. reset
else if(EnaCntrWDT) CntrWDT <= CntrWDT + 1;
end
//if the WDT Counter reset is complete then reset the "counter reset circuit"
always @(negedge CLK)
begin
if(CntrWDT == 0) nReset <= 0;
else nReset <= 1;
if(!EnaCntrWDT) OUT <= 1;
else OUT <= 0;
end

endmodule

• Спасибо за помощь — En_Serg   (15.06.2001 14:23, пустое)