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LAN91C111
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Features
Single Chip Ethernet Controller
Dual Speed - 10/100 Mbps
Fully Supports Full Duplex Switched Ethernet
8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (into Packet Buffer Memory)
Early TX, Early RX Functions
Built-in Transparent Arbitration for Slave Sequential Access Architecture
Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues
3.3V Operation with 5V Tolerant I/O Buffers
Single 25 MHz Reference Clock for Both PHY and MAC
Low Power CMOS Design
Supports Multiple Embedded Processor Host Interfaces
ARM
SH
Power PC
Coldfire
680X0, 683XX
MIPS R3000
3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate
MII Management Serial Interface
128 Pin QFP Package
128 Pin TQFP Package, 1.0 mm Height
Network Interface
Fully Integrated IEEE 802.3/802.3u - 100BASE-TX/10BASE-T Physical Layer
Auto Negotiation: 10/100, Full/Half Duplex
On Chip Wave Shaping - No External Filters Required
Adaptive Equalizer
Baseline Wander Correction
LED Outputs (User Selectable - Up to Two LED Functions at One Time)
E-mail: 
info@telesys.ru
