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обрабатывать сигнал #WAIT в цикле записи / чтения
The active polarity of the WAIT# output is configurable; the state of
CONF[3:0] on the rising edge of RESET# defines the active polarity of
WAIT# for some busses - see “Summary of Configuration Options”.
• For SH-3 Bus, this pin outputs the wait request signal (WAIT#).
• For SH-4 Bus, this pin outputs the ready signal (RDY#).
• For MC68K Bus 1, this pin outputs the data transfer acknowledge
signal (DTACK#).
• For MC68K Bus 2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
• For Generic Bus, this pin outputs the wait signal (WAIT#).
• For MIPS/ISA Bus, this pin outputs the IO channel ready signal
(IOCHRDY).
• For Philips PR31500/31700 Bus, this pin outputs the wait state
signal (/CARDxWAIT).
• For Toshiba TX3912 Bus, this pin outputs the wait state signal
(CARDxWAIT*).
• For PowerPC Bus, this pin outputs the transfer acknowledge signal
(TA#).
• For PC Card (PCMCIA) Bus, this pin outputs the wait signal
(WAIT#).
See Table 4-10, “CPU Interface Pin Mapping,” on page 35 for summary.
See the respective AC Timing diagram for detailed functionality.
Страница 29 Hardware Specification
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