#include "@_PIN_CONNECT.h"
//-----------------------------------------------------------------------------------------------
/**
* Note: LPC2119/2129/2194/2292/2294 configured to operate as SPI master MUST select
* SSEL functionality on an apropriate pin and have HIGH level on this pin in order to act as a master.
*/
class _SPI
{
public://-----------------------------------------------------------------------------------------------
// MODE CPOL CPHA First Data Driven Other Data Driven Data Sampled
// 0 0 0 Prior to 1-st SCK rising edge SCK falling edge SCK rising edge
// 1 0 1 First SCK rising edge SCK rising edge SCK falling edge
// 2 1 0 Prior to 1-st SCK falling edge SCK rising edge SCK falling edge
// 3 1 1 First SCK falling edge SCK falling edge SCK rising edge
//-----------------------------------------------------------------------------------------------
typedef enum
{
//-----------------------------------------------------------------------------------------------
// MODE CPOL CPHA First Data Driven Other Data Driven Data Sampled
// 0 0 0 Prior to 1-st SCK rising edge SCK falling edge SCK rising edge
// ____ ____ ____ ____ ____ ____ ____ ____
// SCK ____| |____| |____| |____| |____| |____| |____| |____| |_________
// _________ _________ _________ _________ _________ _________ _________ _________
// SDO |___MSB___|_________|_________|_________|_________|_________|_________|___LSB___|XXXXXXXXX
// Rx samples ____|_________|_________|_________|_________|_________|_________|_________|______________
MODE0,
//-----------------------------------------------------------------------------------------------
// MODE CPOL CPHA First Data Driven Other Data Driven Data Sampled
// 1 0 1 First SCK rising edge SCK rising edge SCK falling edge
// ____ ____ ____ ____ ____ ____ ____ ____
// SCK ____| |____| |____| |____| |____| |____| |____| |____| |_________
// _________ _________ _________ _________ _________ _________ _________ ______________
// SDO XXXX|___MSB___|_________|_________|_________|_________|_________|_________|___LSB________
// Rx samples _________|_________|_________|_________|_________|_________|_________|_________|_________
MODE1 = (1 << 3),
//-----------------------------------------------------------------------------------------------
// MODE CPOL CPHA First Data Driven Other Data Driven Data Sampled
// 2 1 0 Prior to 1-st SCK falling edge SCK rising edge SCK falling edge
// ____ ____ ____ ____ ____ ____ ____ ____ _________
// SCK |____| |____| |____| |____| |____| |____| |____| |____|
// _________ _________ _________ _________ _________ _________ _________ _________
// SDO |___MSB___|_________|_________|_________|_________|_________|_________|___LSB___|XXXXXXXXX
// Rx samples ____|_________|_________|_________|_________|_________|_________|_________|______________
MODE2,
//-----------------------------------------------------------------------------------------------
// MODE CPOL CPHA First Data Driven Other Data Driven Data Sampled
// 3 1 1 First SCK falling edge SCK falling edge SCK rising edge
// ____ ____ ____ ____ ____ ____ ____ ____ _________
// SCK |____| |____| |____| |____| |____| |____| |____| |____|
// _________ _________ _________ _________ _________ _________ _________ ______________
// SDO XXXX|___MSB___|_________|_________|_________|_________|_________|_________|___LSB________
// Rx samples _________|_________|_________|_________|_________|_________|_________|_________|_________
MODE3
} eTRANSFER_MODE;
typedef enum
{
SLAVE,
MASTER = (1 << 5)
} eMSTR_MODE;
typedef enum
{
MSB_FIRST,
LSB_FIRST = (1 << 6)
} eLSBF_MODE;
//===============================================================================================
//Äîïîëíèòåëüíûå ñèãíàëû SPI
#define RDY IO0PIN_bit.P0_30
#define SS_to_0 IO0CLR_bit.P0_21 = 1
#define SS_to_1 IO0SET_bit.P0_21 = 1
#define AC_to_0 IO0CLR_bit.P0_29 = 1
#define AC_to_1 IO0SET_bit.P0_29 = 1
void SPI0_pin_connect(void)
{ //Ïîäêëþ÷àåì âûâîäû SPI0
PIN.SEL0.P0_4 = PIN.P0_4_SCK0; /* Serial Clock for SPI1. SPI clock output from master or input to slave */
PIN.SEL0.P0_5 = PIN.P0_5_MISO0; /* Master In Slave Out for SPI1. Data input to SPI master or data output from SPI slave */
PIN.SEL0.P0_6 = PIN.P0_6_MOSI0; /* Master Out Slave In for SPI1. Data output from SPI master or data input to SPI slave */
PIN.SEL0.P0_7 = PIN.P0_7_SSEL0; /* Slave Select for SPI1. Selects the SPI interface as a slave */
}
void SPI1_pin_connect(void)
{ //Ïîäêëþ÷àåì âûâîäû SPI1
PIN.SEL1.P0_17 = PIN.P0_17_SCK1; /* Serial Clock for SPI1. SPI clock output from master or input to slave */
PIN.SEL1.P0_18 = PIN.P0_18_MISO1; /* Master In Slave Out for SPI1. Data input to SPI master or data output from SPI slave */
PIN.SEL1.P0_19 = PIN.P0_19_MOSI1; /* Master Out Slave In for SPI1. Data output from SPI master or data input to SPI slave */
PIN.SEL1.P0_20 = PIN.P0_20_SSEL1; /* Slave Select for SPI1. Selects the SPI interface as a slave */
//Ïîäêëþ÷àåì äîïîëíèòåëüíûå ñèãíàëû
PIN.SEL1.P0_21 = PIN.GPIO; // SS
PIN.SEL1.P0_22 = PIN.GPIO; // IRQ
PIN.SEL1.P0_29 = PIN.GPIO; // AC
PIN.SEL1.P0_30 = PIN.GPIO; // RDY
IO0DIR_bit.P0_21 = 1; // SS
IO0DIR_bit.P0_22 = 0; // IRQ
IO0DIR_bit.P0_29 = 1; // AC
IO0DIR_bit.P0_30 = 0; // RDY
//Ïðåäóñòàíîâêà äîïîëíèòåëüíûõ ñèãíàëîâ
SS_to_1;
AC_to_1;
}
void SPI1_config(uint8 mode)
{
SPI1_pin_connect();
S1SPCCR = 50; // set the maximum clock rate (8)
S1SPCR = (uint32)(mode); //Íàñòðàèâàåì MODE
S1SPCR_bit.MSTR = 1; //Âêëþ÷àåì ðåæèì ìàñòåð
}
void SPI1_putchar(uint8 in)
{
S1SPDR = in;
while (! S1SPSR_bit.SPIF) // wait until the character is sent/received SPIF will be cleared automatically
{
if (S1SPSR_bit.MODF == 1)
{
S1SPCR_bit.MSTR = 1;
break;
};
};
}
void reg_write(void)
{
SS_to_0;
//,,,,,,,,,,,,
}
/*
uint8 reg_read(uint8 address)
{
do // Ñáðàâûâàòü è óñòàíàâëèâàòü SS äî òåõ ïîð
{ // ïîêà ìîäåì íå îòâåòèò ÷òî ãîòîâ
SS_to_1;
SS_to_0;
}
while (RDY==1);
// RDY=0 => ìîäåì ãîòîâ ê îáùåíèþ
AC_to_0; // Ïåðåäàåì àäðåñ
address |= (1<<7);
S1SPDR = address;
while (! S1SPSR_bit.SPIF); // wait until the character is sent/received SPIF will be cleared automatically
AC_to_1; // Ïåðåäàåì äàííûå
do // Ñáðàñûâàòü è óñòàíàâëèâàòü SS äî òåõ ïîð
{ // ïîêà ìîäåì íå îòâåòèò ÷òî ãîòîâ
SS_to_1;
SS_to_0;
}
while (RDY==1);
// RDY=0 => ìîäåì ãîòîâ ê îáùåíèþ
S1SPDR = 0; //íèíèöèàëèçàöèÿ ïåðåäà÷è
while (! S1SPSR_bit.SPIF); // wait until the character is sent/received SPIF will be cleared automatically
return S1SPDR;
}
*/
void reg_read(uint8 address)
{
NOP;
}
//===============================================================================================
private:
/**
*
SPI Control Register, +00
* This register controls the operation of the SPI.
*/
volatile union
{
__REG32 All;
struct
{
__REG32 :3;
__REG32 CPHA :1;
__REG32 CPOL :1;
/**
* Master mode select.
* When 1, the SPI operates in Master mode.
* When 0, the SPI operates in Slave mode.
*/
__REG32 MSTR :1; /**
* LSB First controls which direction each byte is shifted when transferred.
* When 1, SPI data is transferred LSB (bit 0) first.
* When 0, SPI data is transferred MSB (bit 7) first.
*/
__REG32 LSBF :1;
/**
* Serial peripheral interrupt enable.
* When 1, a hardware interrupt is generated each time the SPIF or MODF bits are activated.
* When 0, SPI interrupts are inhibited.
*/
__REG32 SPIE :1;
__REG32 :24;
};
} CR;
/**
*
SPI status register, +04
* This register shows the status of the SPI.
*/
volatile union
{
__REG32 All;
struct
{
__REG32 :3; /**
* Slave abort.
* When 1, this bit indicates that a slave abort has occurred.
* This bit is cleared by reading this register.
* Read Overrun - A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the
* processor, and a new transfer has completed. The read buffer containing valid data is indicated by the SPIF bit in the status
* register being active. When a transfer completes, the SPI block needs to move the received data to the read buffer. If the SPIF
* bit is active (the read buffer is full), the new receive data will be lost, and the read overrun (ROVR) bit in the status register will
* be activated.
*/
__REG32 ABRT :1;
/**
* Mode fault.
* When 1, this bit indicates that a Mode fault error has occurred.
* This bit is cleared by reading this register, then writing the SPI control register.
* Mode Fault - The SSEL signal must always be inactive when the SPI block is a master. If the SSEL signal goes active, when
* the SPI block is a master, this indicates another master has selected the device to be a slave. This condition is known as a mode
* fault. When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated, the SPI signal drivers will
* be de-activated, and the SPI mode will be changed to be a SLAVE.
*/
__REG32 MODF :1;
/**
* Read overrun.
* When 1, this bit indicates that a read overrun has occurred.
* This bit is cleared by reading this register.
* Slave Abort - A slave transfer is considered to be aborted, if the SSEL signal goes inactive before the transfer is complete. In
* the event of a slave abort, the transmit and receive data for the transfer that was in progress are lost, and the slave abort (ABRT)
* bit in the status register will be activated.
*/
__REG32 ROVR :1;
/**
* Write collision.
* When 1, this bit indicates that a write collision has occurred.
* This bit is cleared by reading this register, then accessing the SPI data register.
* Write Collision - As stated previously, there is no write buffer between the SPI block bus interface, and the internal shift register.
* As a result, data must not be written to the SPI data register when a SPI data transfer is currently in progress. The time frame
* where data cannot be written to the SPI data register is from when the transfer starts, until after the status register has been read
* when the SPIF status is active. If the SPI data register is written in this time frame, the write data will be lost, and the write collision
* (WCOL) bit in the status register will be activated.
*/
__REG32 WCOL :1;
/**
* SPI transfer complete flag.
* When 1, this bit indicates when a SPI data transfer is complete.
* When a master, this bit is set at the end of the last cycle of the transfer.
* When a slave, this bit is set on the last data sampling edge of the SCK. This bit is
* cleared by first reading this register, then accessing the SPI data register.
* Note: this is not the SPI interrupt flag. This flag is found in the SPINT registrer.
*/
__REG32 SPIF :1;
__REG32 :24;
};
} SR;
/**
*
SPI Data Register, +08
* This bi-directional register provides the transmit and receive data for the SPI.
* Transmit data is provided to the SPI by writing to this register.
* Data received by the SPI can be read from this register.
*/
volatile union
{
__REG32 All;
struct
{
__REG32 DATA :8;
__REG32 :24;
};
} DR; /**
*
SPI Clock Counter Register, +0C
* This register controls the frequency of a master’s SCK.
* The register indicates the number of pclk cycles that make up an SPI clock.
* The value of this register must always be an even number. As a result, bit 0 must always be 0.
* The value of the register must also always be greater than or equal to 8.
* Violations of this can result in unpredictable behavior.
*/
volatile union
{
__REG32 All;
struct
{
__REG32 DATA :8;
__REG32 :24;
};
} CCR; /**
*
Not used, +10...+18
*/
volatile __REG32 NotUsed[3];
/**
* SPI Interrupt Register, +1C
* This register contains the interrupt flag for the SPI interface.
*/
volatile union
{
__REG32 All;
struct
{
/**
* SPI interrupt flag. Set by the SPI interface to generate an interrupt.
* Cleared by writing a 1 to this bit.
* Note: this bit will be set once when SPIE=1 and at least one of SPIF and WCOL bits is 1.
* However, only when SPI Interrupt bit is set and SPI Interrupt is enabled in the VIC,
* SPI based interrupt can be processed by interrupt handling software.
*/
__REG32 SPIINT :1;
__REG32 :31;
};
} INT;
};
//-----------------------------------------------------------------------------------------------
#pragma object_attribute = __no_init
extern _SPI SPI0 @ 0xE0020000;#if (defined(__IOLPC2119_H) || defined(__IOLPC2129_H) || defined(__IOLPC2194_H) || defined(__IOLPC2292_H) || defined(__IOLPC2294_H))
#pragma object_attribute = __no_init
extern _SPI SPI1 @ 0xE0030000;
#endif
//-----------------------------------------------------------------------------------------------
#endif /* _SPI_H_ */
//-----------------------------------------------------------------------------------------------
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