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; AVR assembler
; Target MCU - AT90S2313
; Clock frequency 9.8304 MHz
.def a = r16
.def b = r17
.macro en_7705
cbi portb,cs
.endm
.macro dis_7705
sbi portb,cs
.endm
.macro sclk_hi
sbi portd,sclk
.endm
.macro sclk_lo
cbi portd,sclk
.endm
main:
; Active Channel is Ain2+/Ain2-,
; next operation is write to the clock register
ldi a,$21
rcall movb_7705
; master clock enabled, 4.9512 MHz clock,
; set output rate to 50 Hz
ldi a,$0c
rcall movb_7705
; Active Channel is Ain2+/Ain2-, next
; operation is write to the setup register
ldi a,$11
rcall movb_7705
; gain=2, unipolar mode, buffer on,
; clear FSYNC and perform a self-calibration
ldi a,$46 | (Gain2<<3)
rcall movb_7705
; wait for DRDY signal
sbic pind,drdy
rjmp pc-1
; Read data from Channel Ain2+/Ain2-
ldi a,$39
rcall movb_7705
clr a
rcall movb_7705
std Y+Ain2+0,a
clr a
rcall movb_7705
std Y+Ain2+1,a
;-------------------------------
; Takes 7 cycles
tiny_delay:
ret
;-------------------------------
; Out byte by virtual SPI
; Input data: a-register
; Output data: a-register
; Registers used: a,b
movb_7705:
cli
en_7705
ldi b,8
clock_fall:
sclk_lo
; put bit out
sbrc a,7
sbi portd,dout
sbrs a,7
cbi portd,dout
rcall tiny_delay
; get bit in
lsl a
sbic pind,din
sbr a,1
; clock_rise:
sclk_hi
rcall tiny_delay
dec b
brne clock_fall
dis_7705
sei
ret
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