Error (10839): Verilog HDL error at counter18.v(1): declaring global objects is a SystemVerilog feature
Error (10170): Verilog HDL syntax error at counter18.v(2) near text "always"; expecting an identifier ("always" is a reserved keyword ), or "module", or "macromodule", or "function", or "parameter", or "primitive", or "real", or "realtime", or "reg", or "specparam", or "supply0", or "task", or "time", or "tri", or "tri0", or "tri1", or "triand", or "trior", or "trireg", or "wand", or "wire", or "integer", or "localparam", or "(*", or "config", or "include", or "library"

без сброса:
reg[17:0] counter;
always @(posedge clock)
counter <= counter + 1;

со сбросом:
reg [17:0] cnt;
always @(posedge clk)
if (reset)
cnt <= 0;
else
cnt <= cnt+1;

Тоже самое