module case_test (in, out1, out2);
input [1:0] in;
output [1:0] out1, out2;
reg [1:0] _out1, _out2;

always @*
case (in)
0 : _out1=3;
1 : _out1=2;
2 : _out1=1;
3 : _out1=0;
endcase

always @*
case (in)
0 : _out2=2;
1 : _out2=3;
2 : _out2=0;
3 : _out2=1;
endcase

assign out1=_out1, out2=_out2;
endmodule