Библиотечная функция из lib_twi.c:

/*----------------------------------------------------------------------------
Function : AT91F_TWI_WriteMultipleIadr
Arguments: < AT91PS_TWI pTwi > : Pointer to the TWI structure.
           < SlaveAddr > : Address of the slave device to read from.
           < data > : Pointer to the data to write
           < NumOfBytes > : Number of data to write
Comments : Write multiple data into a slave device with internal address.
           Takes into account the NACK errata.
Return Value: AT91C_TWI_NACK if so.
-----------------------------------------------------------------------------*/
int AT91F_TWI_WriteMultipleIadr(const AT91PS_TWI pTwi,
                                   int SlaveAddr,
                                   int IntAddr,
                                   int IntAddrSize,
                                   char *data,
                                   unsigned int NumOfBytes)
{
 unsigned int end = 0, status, error=0, Count;
 /* Enable Master Mode */
 pTwi -> TWI_CR = AT91C_TWI_MSEN ;
 /* Set the TWI Master Mode Register */
 pTwi -> TWI_MMR =  SlaveAddr | IntAddrSize & ~AT91C_TWI_MREAD;
 /* Set TWI Internal Address Register if needed */
 pTwi -> TWI_IADR = IntAddr;
 /* Wait until TXRDY is high to transmit */
 status = AT91C_BASE_TWI -> TWI_SR;
 while (!(status & AT91C_TWI_TXRDY))
   status = AT91C_BASE_TWI -> TWI_SR;
 /* Send the data */
 for ( Count=0; Count < NumOfBytes ;Count++ )
 {
  /* Write the data to send into THR. Start conditionn DADDR and R/W bit
  are sent automatically */
  AT91C_BASE_TWI -> TWI_THR = *data++;
  /* NACK errata handling */
  /* Do not poll the TWI_SR */
  /* Wait 3 x 9 TWCK pulse (max) before reading TWI_SR */
  /* From 400Khz down to 1Khz, the time to wait will be in µs range.*/
  /* In this example the TWI period is 1/400KHz */
  AT91F_TWI_WaitMicroSecond (40) ;
  while (!end)
  {
   status = AT91C_BASE_TWI -> TWI_SR;
   if ((status & AT91C_TWI_NACK) == AT91C_TWI_NACK)
    {
     error++;
     end=1;
    }
   /*  Wait for the Transmit ready is set */
   if ((status & AT91C_TWI_TXRDY) == AT91C_TWI_TXRDY)
    end=1;
   }
  }
  /* Wait for the Transmit complete is set */
  status = AT91C_BASE_TWI -> TWI_SR;
  while (!(status & AT91C_TWI_TXCOMP))
    status = AT91C_BASE_TWI -> TWI_SR;
  return error;
}

Где START, где STOP?

Про старт написано:
/* Write the data to send into THR. Start conditionn DADDR and R/W bit are sent automatically */

Это действительно так? А STOP???