#ifndef _M8DEF_INC_
#define _M8DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega8
#pragma AVRPART ADMIN PART_NAME ATmega8
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x93
.equ SIGNATURE_002 = 0x07
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ GICR = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ SPMCR = 0x37
.equ TWCR = 0x36
.equ MCUCR = 0x35
.equ MCUCSR = 0x34
.equ TCCR0 = 0x33
.equ TCNT0 = 0x32
.equ OSCCAL = 0x31
.equ SFIOR = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1L = 0x2c
.equ TCNT1H = 0x2d
.equ OCR1AL = 0x2a
.equ OCR1AH = 0x2b
.equ OCR1BL = 0x28
.equ OCR1BH = 0x29
.equ ICR1L = 0x26
.equ ICR1H = 0x27
.equ TCCR2 = 0x25
.equ TCNT2 = 0x24
.equ OCR2 = 0x23
.equ ASSR = 0x22
.equ WDTCR = 0x21
.equ UBRRH = 0x20
.equ UCSRC = 0x20
.equ EEARL = 0x1e
.equ EEARH = 0x1f
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PORTC = 0x15
.equ DDRC = 0x14
.equ PINC = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ SPDR = 0x0f
.equ SPSR = 0x0e
.equ SPCR = 0x0d
.equ UDR = 0x0c
.equ UCSRA = 0x0b
.equ UCSRB = 0x0a
.equ UBRRL = 0x09
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSRA = 0x06
.equ ADCL = 0x04
.equ ADCH = 0x05
.equ TWDR = 0x03
.equ TWAR = 0x02
.equ TWSR = 0x01
.equ TWBR = 0x00
.....
; ***** USART ************************
; UDR - USART I/O Data Register
.equ UDR0 = 0 ; USART I/O Data Register bit 0
.equ UDR1 = 1 ; USART I/O Data Register bit 1
.equ UDR2 = 2 ; USART I/O Data Register bit 2
.equ UDR3 = 3 ; USART I/O Data Register bit 3
.equ UDR4 = 4 ; USART I/O Data Register bit 4
.equ UDR5 = 5 ; USART I/O Data Register bit 5
.equ UDR6 = 6 ; USART I/O Data Register bit 6
.equ UDR7 = 7 ; USART I/O Data Register bit 7
; UCSRA - USART Control and Status Register A
.equ USR = UCSRA ; For compatibility
.equ MPCM = 0 ; Multi-processor Communication Mode
.equ U2X = 1 ; Double the USART transmission speed
.equ UPE = 2 ; Parity Error
.equ PE = UPE ; For compatibility
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; USART Data Register Empty
.equ TXC = 6 ; USART Transmitt Complete
.equ RXC = 7 ; USART Receive Complete
; UCSRB - USART Control and Status Register B
.equ UCR = UCSRB ; For compatibility
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ UCSZ2 = 2 ; Character Size
.equ CHR9 = UCSZ2 ; For compatibility
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
; UCSRC - USART Control and Status Register C
.equ UCPOL = 0 ; Clock Polarity
.equ UCSZ0 = 1 ; Character Size
.equ UCSZ1 = 2 ; Character Size
.equ USBS = 3 ; Stop Bit Select
.equ UPM0 = 4 ; Parity Mode Bit 0
.equ UPM1 = 5 ; Parity Mode Bit 1
.equ UMSEL = 6 ; USART Mode Select
.equ URSEL = 7 ; Register Select
.equ UBRRHI = UBRRH ; For compatibility
