1. UART Module
The 16x baud clock signal on the BCLK pin is
present only when the module is transmitting.
2. UART Module
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
3. SPI Module
The SPI transmit buffer full (SPITBF) flag does not
get set immediately after writing to the buffer.
4. SPI Module in Frame Master Mode
The SPI module will generate incorrect frame
synchronization pulses in Frame Master mode if
FRMDLY = 1.
2
C™ Module
5. I
The BCL bit in I2CSTAT can only be cleared with
Word instructions, and can be corrupted with byte
instructions and bit operations.
2
C Module
6. I
The ACKSTAT bit is cleared shortly after being set
following a slave transmit.
2
C Module: 10-bit Addressing Mode
7. I
2
C module is configured for 10-bit
When the I
addressing using the same address bits (A10 and
2
C devices, the A10 and A9 bits may
A9) as other I
not work as expected.
2
C Module: 10-bit Addressing Mode
8. I
2
C module is configured as a 10-bit
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
2
C Module
9. I
2
C module enabled, the PORT bits and
With the I
external Interrupt Input functions (if any)
associated with SCL and SDA pins will not reflect
the actual digital logic levels on the pins.
2
10. I C Module: 10-bit Addressing Mode
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
11. UART (UxE Interrupt)
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
12. UART Module
When the UART module is operating in 8-bit mode
®
encoder/
(PDSEL = 0x) and using the IrDA
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
13. Comparator Module
When CMCON<CxOUTEN> is set, the
Comparator output pin cannot be used as a
General Purpose I/O pins even if the Comparator
is disabled.
14. Internal Voltage Regulator
When the VREGS (RCON<8>) bit is set to a logic
‘0’ higher sleep current may be observed.
15. Product Identification
Revision A2 devices marked as extended
temperature range (E) devices, support only
industrial temperature range (I).
16. PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
17. ECAN Module
The ECAN module may not store received data in
the correct location.
18. ECAN Module
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set.