Отправлено yura_POL 29 августа 2002 г. 21:03 В ответ на: Помогите ссылочкой (+) отправлено hotson 29 августа 2002 г. 13:51

/***********************************************************************
* unsigned long ldivp(unsigned long * num, unsigned long denom);
* divides num by denom. unsigned;
* r16-r17 -- *num; r20-r23 -- denom
* Code: 50 clocks: 716
* divides *num, returns remainder,
************************************************************************/
ENTRY ldivp
MOV16 r30, r31, r16, r17
st -Y, r24
ldi r24, 0x21
ldd r16, Z+0
ldd r17, Z+1
ldd r18, Z+2
ldd r19, Z+3
clr r0
clr r1
clr r2
clr r3
mldiv_0:
dec r24
breq mldiv_2
rol r16
rol r17
rol r18
rol r19
rol r0
rol r1
rol r2
rol r3
cp r0, r20
cpc r1, r21
cpc r2, r22
cpc r3, r23
brcs mldiv_0
sub r0, r20 /* actual division */
sbc r1, r21 /* C=0 will be shifted in r16 */
sbc r2, r22
sbc r3, r23
rjmp mldiv_0
mldiv_2:
rol r16
rol r17 /* shift off initial C value */
rol r18
rol r19
com r16
com r17 /* because result was inversed */
com r18
com r19
std Z+0, r16
std Z+1, r17
std Z+2, r18
std Z+3, r19
MOV16 r16, r17, r0, r1
MOV16 r18, r19, r2, r3
ld r24, Y+
ret

/***********************************************************************
* unsigned long cldiv(unsigned long num, unsigned long denom);
* divides num by denom, unsigned, rounds;
* r16-r19 -- num; r20-r23 -- denom
* Code: 50 clocks: 716
* returns divided value
************************************************************************/
ENTRY cldiv
st -Y, r24
ldi r24, 0x21
clr r0
clr r1
clr r2
clr r3
cldiv_0:
dec r24
breq cldiv_2
rol r16
rol r17
rol r18
rol r19
rol r0
rol r1
rol r2
rol r3
cp r0, r20
cpc r1, r21
cpc r2, r22
cpc r3, r23
brcs cldiv_0
sub r0, r20 /* actual division */
sbc r1, r21 /* C=0 will be shifted in r16 */
sbc r2, r22
sbc r3, r23
rjmp cldiv_0
cldiv_2:
rol r16
rol r17 /* shift off initial C value */
rol r18
rol r19
com r16
com r17 /* because result was inversed */
com r18
com r19

lsl r0
rol r1
rol r2
rol r3
cp r0, r20
cpc r1, r21 /* 2*remainder - denom */
cpc r2, r22
cpc r3, r23
brcs cldiv_end
subi r16, -1
sbci r17, -1
sbci r18, -1
sbci r19, -1
cldiv_end:
ld r24, Y+
ret
#ifndef HAVE_ARCH_MUL

/***********************************************************************
* unsigned long mmul(unsigned long mul1, unsigned mul2);
*
* r16, r17, r18, r19 -- mul1; r20, r21 -- mul2
* Code: 27 clocks: 254
* returns r16,r17, r18, r19 -- mul1*mul2
************************************************************************/
ENTRY mmul
clr r0
clr r1
clr r2
clr r3 /* who's the fuck made mmul return long? -up... */
mmul_0:
lsr r21
ror r20
brcc mmul_2
add r0, r16
adc r1, r17
adc r2, r18
adc r3, r19
mmul_2:
lsl r16
rol r17
rol r18
rol r19
cpi r20, 0x00
cpc r21, r20
brne mmul_0
mmul_1:
MOV16 r16, r17, r0, r1
MOV16 r18, r19, r2, r3
ret

#else
/* AVR enhanced core */
/* Code: 19 clocks: 26 */
ENTRY mmul
clr r18
clr r19
clr r3
mul r16, r20
MOV16 r22, r23, r0, r1
mul r17, r20
add r23, r0
adc r18, r1
mul r16, r21
add r23, r0
adc r18, r1
adc r19, r3
mul r17, r21
add r18, r0
adc r19, r1
MOV16 r16, r17, r22, r23
ret
#endif