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The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. The external I/O pins do not go high immediately, but will go high within four system clock cycles
after entering the reset state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits
the reset state. This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST
pin is driven low until the end of the VDD reset timeout.
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