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//Test AT91R40008 //===============-VARIABLES DISCRIPTIONS-=========== void main(void) //===========================-EBI for FLASH MBM29LV800TA 1Mbyte(1Mx8/512Kx16)bit-===== alfa=(char*)0x20000000; //============================-PIO INIT-===================== if (*alfa==1) { }//end main
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#include
#include
int i,b;
char *alfa;
{
__EBI_RCR_bit.rcb=1; //REMAP command
//============================-INICIALIZATION-================
__EBI_CSR0_bit.ba=0x010; //hight bit of the base address 010
__EBI_CSR0_bit.dbw=1; // 16-bit data bus width
__EBI_CSR0_bit.nws=7; //Number of standart Wait States NWS=1,1,1 (8)
__EBI_CSR0_bit.wse=1; // WSE=1; Wait state generation is enable
__EBI_CSR0_bit.pages=0; //PAGES=0,0->1Mbyte, Page Size 1Mbyte
__EBI_CSR0_bit.tdf=7; //TDF=1,1,1, 7-> Cycles dded after the Transfer
__EBI_CSR0_bit.bat=0; // BAT=0; Byte -write access type
__EBI_CSR0_bit.csen=1; // CSEN=1; Chip select Enable
//===========================-EBI for SRAM K6R4008V1D 512Kx8bit-===============
//base address external SRAM =0x02000000 for NCS2--> K6R4008V1D
__EBI_CSR2_bit.ba=0x200; //hight bit of the base address 200
__EBI_CSR2_bit.dbw=2; // 8-bit data bus width
__EBI_CSR2_bit.nws=7; //Number of standart Wait States NWS=1,1,1 (8)
__EBI_CSR2_bit.wse=1; // WSE=1; Wait state generation is enable
__EBI_CSR2_bit.pages=0; //PAGES=0,0->1Mbyte, Page Size 1Mbyte
__EBI_CSR2_bit.tdf=7; //TDF=1,1,1, 7-> Cycles dded after the Transfer
__EBI_CSR2_bit.bat=0; // BAT=0; Byte -write access type
__EBI_CSR2_bit.csen=1; // CSEN=1; Chip select Enable
*alfa=1; // *alfa--> To setup value to the address
__PIO_PER_bit.p23=1;
__PIO_OER_bit.p23=1;
//===================-WORK part program-================
while(1)
{
__PIO_SODR_bit.p23=1;
for (i=0;i<=10000;i++) b=0;
__PIO_CODR_bit.p23=1;
for (i=0;i<=10000;i++) b=0;
}
}//end main WHILE
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