Отправлено JTAG 17 августа 2003 г. 16:32 В ответ на: покажи дизасм этого куска кода отправлено Джан Франко Дзолла 17 августа 2003 г. 15:30

######################################################################
# #
# IAR ARM ANSI C/EC++ Compiler V3.21A/W32 EVALUATION 17/Aug/2003 16:14:36 #
# Copyright 1999-2002 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = E:\IARAT91New\myproject\testcstsrtup\170803testLED.c #
# Command line = -I E:\IARAT91New\ARM\INC\ -lC e:\Release\List\ -la #
# e:\Release\List\ -o e:\Release\Obj\ -e -z0 #
# --cpu_mode arm --code_model small --endian little #
# --cpu ARM7TDMI --stack_align 4 --interwork #
# E:\IARAT91New\myproject\testcstsrtup\170803testLED.c #
# List file = e:\Release\List\170803testLED.lst #
# Object file = e:\Release\Obj\170803testLED.r79 #
# #
# #
######################################################################

E:\IARAT91New\myproject\testcstsrtup\170803testLED.c
1 //Test AT91R40008
2 #include
3 #include
4
5 //===============-VARIABLES DISCRIPTIONS-===========

\ In segment HUGE_Z, align 4, align-sorted
6 int i,b;
\ i:
\ 00000000 DS8 4

\ In segment HUGE_Z, align 4, align-sorted
\ `b`:
\ 00000000 DS8 4

\ In segment HUGE_Z, align 4, align-sorted
7 char *alfa;
\ alfa:
\ 00000000 DS8 4
8

\ In segment NEARFUNC_A, align 4, keep-with-next
\ 00000000 CODE32
9 void main(void)
10 {
11 __EBI_RCR_bit.rcb=1; //REMAP command
\ main??rA:
\ main:
\ 00000000 7C029FE5 LDR R0,??main_0 ;; #+0xFFE00020
\ 00000004 001090E5 LDR R1,[R0, #+0]
\ 00000008 011081E3 ORR R1,R1,#+0x1
\ 0000000C 001080E5 STR R1,[R0, #+0]
12 //============================-INICIALIZATION-================
13
14 //===========================-EBI for FLASH MBM29LV800TA 1Mbyte(1Mx8/512Kx16)bit-=====
15 __EBI_CSR0_bit.ba=0x010; //hight bit of the base address 010
\ 00000010 FE06A0E3 MOV R0,#+0xFE00000
\ 00000014 F00480E2 ADD R0,R0,#+0xF0000000
\ 00000018 001090E5 LDR R1,[R0, #+0]
\ 0000001C 0106A0E1 MOV R0,R1, LSL #+12
\ 00000020 2006B0E1 MOVS R0,R0, LSR #+12
\ 00000024 010490E3 ORRS R0,R0,#+0x1000000
\ 00000028 FE16A0E3 MOV R1,#+0xFE00000
\ 0000002C F01481E2 ADD R1,R1,#+0xF0000000
\ 00000030 000081E5 STR R0,[R1, #+0]
16 __EBI_CSR0_bit.dbw=1; // 16-bit data bus width
\ 00000034 FE06A0E3 MOV R0,#+0xFE00000
\ 00000038 F00480E2 ADD R0,R0,#+0xF0000000
\ 0000003C 001090E5 LDR R1,[R0, #+0]
\ 00000040 0300E0E3 MVN R0,#+0x3
\ 00000044 010010E0 ANDS R0,R0,R1
\ 00000048 010090E3 ORRS R0,R0,#+0x1
\ 0000004C FE16A0E3 MOV R1,#+0xFE00000
\ 00000050 F01481E2 ADD R1,R1,#+0xF0000000
\ 00000054 000081E5 STR R0,[R1, #+0]
17 __EBI_CSR0_bit.nws=7; //Number of standart Wait States NWS=1,1,1 (8)
\ 00000058 FE06A0E3 MOV R0,#+0xFE00000
\ 0000005C F00480E2 ADD R0,R0,#+0xF0000000
\ 00000060 001090E5 LDR R1,[R0, #+0]
\ 00000064 1C1081E3 ORR R1,R1,#+0x1C
\ 00000068 001080E5 STR R1,[R0, #+0]
18 __EBI_CSR0_bit.wse=1; // WSE=1; Wait state generation is enable
\ 0000006C FE06A0E3 MOV R0,#+0xFE00000
\ 00000070 F00480E2 ADD R0,R0,#+0xF0000000
\ 00000074 001090E5 LDR R1,[R0, #+0]
\ 00000078 201081E3 ORR R1,R1,#+0x20
\ 0000007C 001080E5 STR R1,[R0, #+0]
19 __EBI_CSR0_bit.pages=0; //PAGES=0,0->1Mbyte, Page Size 1Mbyte
\ 00000080 060DE0E3 MVN R0,#+0x180
\ 00000084 FE16A0E3 MOV R1,#+0xFE00000
\ 00000088 F01481E2 ADD R1,R1,#+0xF0000000
\ 0000008C 002091E5 LDR R2,[R1, #+0]
\ 00000090 002002E0 AND R2,R2,R0
\ 00000094 002081E5 STR R2,[R1, #+0]
20 __EBI_CSR0_bit.tdf=7; //TDF=1,1,1, 7-> Cycles dded after the Transfer
\ 00000098 FE06A0E3 MOV R0,#+0xFE00000
\ 0000009C F00480E2 ADD R0,R0,#+0xF0000000
\ 000000A0 001090E5 LDR R1,[R0, #+0]
\ 000000A4 0E1C81E3 ORR R1,R1,#+0xE00
\ 000000A8 001080E5 STR R1,[R0, #+0]
21 __EBI_CSR0_bit.bat=0; // BAT=0; Byte -write access type
\ 000000AC 010AE0E3 MVN R0,#+0x1000
\ 000000B0 FE16A0E3 MOV R1,#+0xFE00000
\ 000000B4 F01481E2 ADD R1,R1,#+0xF0000000
\ 000000B8 002091E5 LDR R2,[R1, #+0]
\ 000000BC 002002E0 AND R2,R2,R0
\ 000000C0 002081E5 STR R2,[R1, #+0]
22 __EBI_CSR0_bit.csen=1; // CSEN=1; Chip select Enable
\ 000000C4 FE06A0E3 MOV R0,#+0xFE00000
\ 000000C8 F00480E2 ADD R0,R0,#+0xF0000000
\ 000000CC 001090E5 LDR R1,[R0, #+0]
\ 000000D0 021A81E3 ORR R1,R1,#+0x2000
\ 000000D4 001080E5 STR R1,[R0, #+0]
23 //===========================-EBI for SRAM K6R4008V1D 512Kx8bit-===============
24 //base address external SRAM =0x02000000 for NCS2--> K6R4008V1D
25 __EBI_CSR2_bit.ba=0x200; //hight bit of the base address 200
\ 000000D8 A8019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 000000DC 001090E5 LDR R1,[R0, #+0]
\ 000000E0 0106A0E1 MOV R0,R1, LSL #+12
\ 000000E4 2006B0E1 MOVS R0,R0, LSR #+12
\ 000000E8 200490E3 ORRS R0,R0,#+0x20000000
\ 000000EC 94119FE5 LDR R1,??main_0+4 ;; #+0xFFE00008
\ 000000F0 000081E5 STR R0,[R1, #+0]
26 __EBI_CSR2_bit.dbw=2; // 8-bit data bus width
\ 000000F4 8C019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 000000F8 001090E5 LDR R1,[R0, #+0]
\ 000000FC 0300E0E3 MVN R0,#+0x3
\ 00000100 010010E0 ANDS R0,R0,R1
\ 00000104 020090E3 ORRS R0,R0,#+0x2
\ 00000108 78119FE5 LDR R1,??main_0+4 ;; #+0xFFE00008
\ 0000010C 000081E5 STR R0,[R1, #+0]
27 __EBI_CSR2_bit.nws=7; //Number of standart Wait States NWS=1,1,1 (8)
\ 00000110 70019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 00000114 001090E5 LDR R1,[R0, #+0]
\ 00000118 1C1081E3 ORR R1,R1,#+0x1C
\ 0000011C 001080E5 STR R1,[R0, #+0]
28 __EBI_CSR2_bit.wse=1; // WSE=1; Wait state generation is enable
\ 00000120 60019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 00000124 001090E5 LDR R1,[R0, #+0]
\ 00000128 201081E3 ORR R1,R1,#+0x20
\ 0000012C 001080E5 STR R1,[R0, #+0]
29 __EBI_CSR2_bit.pages=0; //PAGES=0,0->1Mbyte, Page Size 1Mbyte
\ 00000130 060DE0E3 MVN R0,#+0x180
\ 00000134 4C119FE5 LDR R1,??main_0+4 ;; #+0xFFE00008
\ 00000138 002091E5 LDR R2,[R1, #+0]
\ 0000013C 002002E0 AND R2,R2,R0
\ 00000140 002081E5 STR R2,[R1, #+0]
30 __EBI_CSR2_bit.tdf=7; //TDF=1,1,1, 7-> Cycles dded after the Transfer
\ 00000144 3C019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 00000148 001090E5 LDR R1,[R0, #+0]
\ 0000014C 0E1C81E3 ORR R1,R1,#+0xE00
\ 00000150 001080E5 STR R1,[R0, #+0]
31 __EBI_CSR2_bit.bat=0; // BAT=0; Byte -write access type
\ 00000154 010AE0E3 MVN R0,#+0x1000
\ 00000158 28119FE5 LDR R1,??main_0+4 ;; #+0xFFE00008
\ 0000015C 002091E5 LDR R2,[R1, #+0]
\ 00000160 002002E0 AND R2,R2,R0
\ 00000164 002081E5 STR R2,[R1, #+0]
32 __EBI_CSR2_bit.csen=1; // CSEN=1; Chip select Enable
\ 00000168 18019FE5 LDR R0,??main_0+4 ;; #+0xFFE00008
\ 0000016C 001090E5 LDR R1,[R0, #+0]
\ 00000170 021A81E3 ORR R1,R1,#+0x2000
\ 00000174 001080E5 STR R1,[R0, #+0]
33
34 alfa=(char*)0x20000000;
\ 00000178 2004A0E3 MOV R0,#+0x20000000
\ 0000017C 08119FE5 LDR R1,??main_0+8 ;; #alfa
\ 00000180 000081E5 STR R0,[R1, #+0]
35 *alfa=1; // *alfa--> To setup value to the address
\ 00000184 0100A0E3 MOV R0,#+0x1
\ 00000188 FC109FE5 LDR R1,??main_0+8 ;; #alfa
\ 0000018C 002091E5 LDR R2,[R1, #+0]
\ 00000190 0000C2E5 STRB R0,[R2, #+0]
36
37 //============================-PIO INIT-=====================
38 __PIO_PER_bit.p23=1;
\ 00000194 FF08A0E3 MOV R0,#+0xFF0000
\ 00000198 FF0480E2 ADD R0,R0,#+0xFF000000
\ 0000019C 001090E5 LDR R1,[R0, #+0]
\ 000001A0 021581E3 ORR R1,R1,#+0x800000
\ 000001A4 001080E5 STR R1,[R0, #+0]
39 __PIO_OER_bit.p23=1;
\ 000001A8 EF00E0E3 MVN R0,#+0xEF
\ 000001AC FF0C40E2 SUB R0,R0,#+0xFF00
\ 000001B0 001090E5 LDR R1,[R0, #+0]
\ 000001B4 021581E3 ORR R1,R1,#+0x800000
\ 000001B8 001080E5 STR R1,[R0, #+0]
40 //===================-WORK part program-================
41 while(1)
42 {
43
44 if (*alfa==1) {
\ ??main_1:
\ 000001BC C8009FE5 LDR R0,??main_0+8 ;; #alfa
\ 000001C0 001090E5 LDR R1,[R0, #+0]
\ 000001C4 0000D1E5 LDRB R0,[R1, #+0]
\ 000001C8 FF0010E2 ANDS R0,R0,#+0xFF ;; Zero extend
\ 000001CC 010050E3 CMP R0,#+0x1
\ 000001D0 F9FFFF1A BNE ??main_1
45 __PIO_SODR_bit.p23=1;
\ 000001D4 CF00E0E3 MVN R0,#+0xCF
\ 000001D8 FF0C40E2 SUB R0,R0,#+0xFF00
\ 000001DC 001090E5 LDR R1,[R0, #+0]
\ 000001E0 021581E3 ORR R1,R1,#+0x800000
\ 000001E4 001080E5 STR R1,[R0, #+0]
46 for (i=0;i<=10000;i++) b=0;
\ 000001E8 0000A0E3 MOV R0,#+0x0
\ 000001EC A0109FE5 LDR R1,??main_0+16 ;; #i
\ 000001F0 000081E5 STR R0,[R1, #+0]
\ 000001F4 060000EA B ??main_2
\ ??main_3:
\ 000001F8 0000A0E3 MOV R0,#+0x0
\ 000001FC 8C109FE5 LDR R1,??main_0+12 ;; #`b`
\ 00000200 000081E5 STR R0,[R1, #+0]
\ 00000204 88009FE5 LDR R0,??main_0+16 ;; #i
\ 00000208 001090E5 LDR R1,[R0, #+0]
\ 0000020C 011081E2 ADD R1,R1,#+0x1
\ 00000210 001080E5 STR R1,[R0, #+0]
\ ??main_2:
\ 00000214 78009FE5 LDR R0,??main_0+16 ;; #i
\ 00000218 001090E5 LDR R1,[R0, #+0]
\ 0000021C 1100A0E3 MOV R0,#+0x11
\ 00000220 270C80E2 ADD R0,R0,#+0x2700
\ 00000224 000051E1 CMP R1,R0
\ 00000228 F2FFFFBA BLT ??main_3
47 __PIO_CODR_bit.p23=1;
\ 0000022C CB00E0E3 MVN R0,#+0xCB
\ 00000230 FF0C40E2 SUB R0,R0,#+0xFF00
\ 00000234 001090E5 LDR R1,[R0, #+0]
\ 00000238 021581E3 ORR R1,R1,#+0x800000
\ 0000023C 001080E5 STR R1,[R0, #+0]
48 for (i=0;i<=10000;i++) b=0;
\ 00000240 0000A0E3 MOV R0,#+0x0
\ 00000244 48109FE5 LDR R1,??main_0+16 ;; #i
\ 00000248 000081E5 STR R0,[R1, #+0]
\ ??main_4:
\ 0000024C 40009FE5 LDR R0,??main_0+16 ;; #i
\ 00000250 001090E5 LDR R1,[R0, #+0]
\ 00000254 1100A0E3 MOV R0,#+0x11
\ 00000258 270C80E2 ADD R0,R0,#+0x2700
\ 0000025C 000051E1 CMP R1,R0
\ 00000260 D5FFFFAA BGE ??main_1
\ 00000264 0000A0E3 MOV R0,#+0x0
\ 00000268 20109FE5 LDR R1,??main_0+12 ;; #`b`
\ 0000026C 000081E5 STR R0,[R1, #+0]
\ 00000270 1C009FE5 LDR R0,??main_0+16 ;; #i
\ 00000274 001090E5 LDR R1,[R0, #+0]
\ 00000278 011081E2 ADD R1,R1,#+0x1
\ 0000027C 001080E5 STR R1,[R0, #+0]
\ 00000280 F1FFFFEA B ??main_4
\ 00000284 DATA
\ ??main_0:
\ 00000284 2000E0FF DC32 +0xFFE00020
\ 00000288 0800E0FF DC32 +0xFFE00008
\ 0000028C ........ DC32 alfa
\ 00000290 ........ DC32 `b`
\ 00000294 ........ DC32 i
49 }
50 }//end main WHILE
51
52 }//end main

\ In segment HUGE_AN, at 0xffe00000
\ union volatile __huge _A___EBI_CSR0
\ _A___EBI_CSR0:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffe00008
\ union volatile __huge _A___EBI_CSR2
\ _A___EBI_CSR2:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffe00020
\ union volatile __huge _A___EBI_RCR
\ _A___EBI_RCR:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffff0000
\ union volatile __huge _A___PIO_PER
\ _A___PIO_PER:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffff0010
\ union volatile __huge _A___PIO_OER
\ _A___PIO_OER:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffff0030
\ union volatile __huge _A___PIO_SODR
\ _A___PIO_SODR:
\ 00000000 DS8 4

\ In segment HUGE_AN, at 0xffff0034
\ union volatile __huge _A___PIO_CODR
\ _A___PIO_CODR:
\ 00000000 DS8 4
53

Maximum stack usage in bytes:

Function CSTACK
-------- ------
main 0

28 bytes in segment HUGE_AN
12 bytes in segment HUGE_Z
12 bytes in segment INITTAB
668 bytes in segment NEARFUNC_A

668 bytes of CODE memory (+ 12 bytes shared)
12 bytes of HUGEDATA memory (+ 28 bytes shared)

Errors: none
Warnings: none