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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--=============================================================================
ENTITY test IS
GENERIC (WIDTH : integer :=16);
PORT (
DATA : IN std_logic_vector (15 downto 0);
RST : IN std_logic;
CLK : IN std_logic;
OE : IN std_logic;
Q : INOUT std_logic_vector(15 downto 0)
);
END test ;
--=============================================================================
ARCHITECTURE behv OF test IS
BEGIN
--=============================================================================
PROCESS(Clk,OE, rst)
BEGIN
if(rst = '0') then
Q <= "0000000000000000";
elsif (Clk'event and Clk = '1') then
if(OE = '1') then
Q <= DATA;
else
Q <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
END PROCESS;
--=============================================================================
END behv;
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