|
Вот: Compiling source files... Simulating partition 1 Reading netlist... Simulation FAILED due to fatal simulator errors.
E-mail:
info@telesys.ru
SIMULATION LOG
==============
Design: UNTITLED.DSN
Doc. no.:
Revision:
Author:
Created: 06/27/04
Modified: 06/27/04
Build completed OK.
Compiling netlist...
Linking netlist...
Partition analysis...
PROSPICE Release 6.5 SP2 (C) Labcenter Electronics 1993-2002.
SPICE Kernel Version 3f5. (C) Berkeley University ERL.
ERROR: [U1] mixed model PIC18.DLL failed to authorize - Bad or missing Customer Key.
Net VDD taken as alias for VCC
Net VSS taken as alias for GND
Reading SPICE models...
Loading library 'ANALOGD.SML'
Loading library 'APEX.SML'
Loading library 'BURRBROWN.SML'
Loading library 'ELANTEC.SML'
Loading library 'FAIRCHLD.SML'
Loading library 'INTERSIL.SML'
Loading library 'LINTEC.SML'
Loading library 'NATOA.SML'
Loading library 'SUPERTEX.SML'
Loading library 'TECCOR.SML'
Loading library 'TEX101.SML'
Loading library 'TEX301.SML'
Loading library 'TEX3_1.SML'
Loading library 'TEX401.SML'
Loading library 'TEX5_1.SML'
Loading library 'VALVES.SML'
Loading library 'ZETEX.SML'
Building circuit...
Adding +5V power rail for VCC
Instantiating SPICE models...
Real Time Simulation failed to start
Ответы