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entity WAIT_ON is
port(
clk_in : in std_logic;
clk_out : out std_logic
);
end;
--======================= ARCHITECTURE ==================================
architecture RTL of WAIT_ON is
signal Q1: std_logic;
signal Q2: std_logic;
signal Q: std_logic;
begin
process
begin
wait until falling_edge(clk_in);
Q1 <= Q2;
end process;
process
begin
wait until rising_edge(clk_in);
Q2 <= not Q1;
end process;
Q <= Q1 xor Q2;
clk_out <= (clk_in and not Q) or (not clk_in and Q);
end;
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