Отправлено NickS. 18 февраля 2003 г. 10:52 В ответ на: Ответ: отправлено _Lexx_ 18 февраля 2003 г. 08:20

Например так

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test is
port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR (1 downto 0);
OUTP: out STD_LOGIC
);
end test;

architecture behave of test is

signal dat: STD_LOGIC_VECTOR (1 downto 0);
signal ou: STD_LOGIC ;
begin

pclk: process (clk)
begin
if reset='0' then
ou<='0';
elsif clk'event and clk='1' then
if (DATA xor dat)="00" then
ou<='0';
else
ou<='1';
dat<=DATA;
end if;
end if;
end process;
OUTP<=ou;
end behave ;

или так

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test is
port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
DATA: in STD_LOGIC_VECTOR (1 downto 0);
OUTP: out STD_LOGIC
);
end test;

architecture behave of test is

signal timer: STD_LOGIC_VECTOR(15 downto 0) ;
signal dat: STD_LOGIC_VECTOR (1 downto 0);
signal ou: STD_LOGIC ;
begin

pclk: process (clk)
begin
if reset='0' then
timer<="0000000000000000";
ou<='0';
dat<="00";
elsif timer= "0000000000000100" then
dat<=DATA;
ou<='1';
elsif clk'event and clk='1' then
if (DATA xor dat)="00" then
timer<="0000000000000000";
else
timer<=timer+'1';
end if;
end if;
end process;
OUTP<=ou;
end behave ;

Не совсем ясно, что нужно