Отправлено Aldec 25 февраля 2003 г. 15:49 В ответ на: А у Вас какая среда разработки. Там иногда и визард есть. отправлено KA 25 февраля 2003 г. 15:39

library IEEE;
use IEEE.std_logic_1164.all;

entity shft_reg is
port (
DIR : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
SI : in std_logic;
DATA : in std_logic_vector(7 downto 0);
O : out std_logic_vector(7 downto 0)
);
end entity;

--}} End of automatically maintained section

architecture shft_reg_arch of shft_reg is
signal TEMP_O : std_logic_vector(7 downto 0);
begin

process(CLK, CLR, SET)
begin
if CLR = '1' then
TEMP_O <= "00000000";
elsif SET = '1' then
TEMP_O <= "11111111";
elsif rising_edge(CLK) then
if CE = '1' then
if LOAD = '1' then
TEMP_O <= DATA;
else
if DIR = '1' then
TEMP_O <= SI & TEMP_O(7 downto 1);
else
TEMP_O <= TEMP_O(6 downto 0) & SI;
end if;
end if;
end if;
end if;
end process;

O <= TEMP_O;

end architecture;

library IEEE;
use IEEE.std_logic_1164.all;

entity shft_reg_syn is
port (
DIR : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
SI : in std_logic;
DATA : in std_logic_vector(7 downto 0);
O : out std_logic_vector(7 downto 0)
);
end entity;

--}} End of automatically maintained section

architecture shft_reg_arch of shft_reg_syn is
signal TEMP_O : std_logic_vector(7 downto 0);
begin

process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
if CLR = '1' then
TEMP_O <= "00000000";
elsif SET = '1' then
TEMP_O <= "11111111";
elsif LOAD = '1' then
TEMP_O <= DATA;
else
if DIR = '1' then
TEMP_O <= SI & TEMP_O(7 downto 1);
else
TEMP_O <= TEMP_O(6 downto 0) & SI;
end if;
end if;
end if;
end if;
end process;

O <= TEMP_O;

end architecture;