[an error occurred while processing this directive]
...........always @ (posedge clk)begin if (B_int[19:8]>'d1023) B_sat[9:0]<='d1023; else B_sat[9:0]<=B_int[17:8];//результат endassign B = B_sat[9:0];endmodule
assign B = B_sat[9:0];
endmodule
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