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Есть проблемы при работе с ISE.
Пример:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY top IS
port(
arstn : in std_logic;
clk : in std_logic;
wr : in std_logic;
data : in std_logic_vector(0 to 15);
q : out std_logic_vector(15 downto 0)
);
END top ;
ARCHITECTURE behave OF top IS
BEGIN
process (arstn, clk)
begin
if (arstn = '0') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
if (wr = '1') then
q <= data;
end if;
end if;
end process;
END behave;
После создания "Post-Place & Route Simulation Model" было обнаружено в "top_timesim.vhd" следующее:
entity top is
port (
clk : in STD_LOGIC := 'X';
wr : in STD_LOGIC := 'X';
arstn : in STD_LOGIC := 'X';
data : in STD_LOGIC_VECTOR ( 15 downto 0 );
q : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end top;
Вопрос с какой стати входная шина "data : in std_logic_vector(0 to 15)" превратилась в "data : in STD_LOGIC_VECTOR (15 downto 0);"?
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