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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY drebezg IS
PORT(but_in,clk : IN STD_LOGIC;
but_out : OUT STD_LOGIC);
END drebezg;
ARCHITECTURE but OF drebezg IS
SIGNAL reg_but : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL (clk'EVENT) AND (clk = '1');
reg_but(2 DOWNTO 0) <= reg_but(3 DOWNTO 1);
reg_but(3) <= but_in;
IF reg_but(3 DOWNTO 0)="0000" THEN
but_out <= '0';
ELSE
but_out <= '1';
END IF;
END PROCESS;
END but;
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