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ну не люблю я писать много...
signal LMX_OUT : std_logic_vector(21 downto 0); -- spi regs
signal SI_OUT : std_logic_vector(21 downto 0); -- spi regs
signal RF_ADDR : std_logic_vector(8 downto 0); -- R/W AI addr(6:0)
signal RF_OUT : std_logic_vector(7 downto 0); -- spi regs
signal RF_IN : std_logic_vector(7 downto 0); -- spi regs
--------
process (CLK, RST)
begin
if RST = '1' then
(LMX_OUT,SI_OUT,RF_ADDR,RF_OUT,DATA_OUT) <= (others=>'0');
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