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Время умножения операндов разрядности n и m равно n+m тактов.
Места занимает меньше чем * c набором входных и выходных регистров.
Частоту тоже можно сильно разогнать.
VHDL выглядит примерно так.
--------------------------------------------------------------------------
-- Filename : SHIFT_MULT.vhd
--
-- Author(s): Pavel Matyushin
--
-- Written : Pavel Matyushin
-- Modified : Pavel Matyushin
-- Subject :
--
-- Version : 0.1
-- Last Modified : 23.06.2002
--
-- Description : Shift Register Based Multiplier
-------------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity SHIFT_MULT is
generic (A_Size : integer := 15;
B_SiZe : integer := 15);
port (
RESET : in std_logic;
CLOCK : in std_logic;
LOAD : in std_logic;
A : in std_logic_vector(A_Size - 1 downto 0);
B : in std_logic_vector(B_Size - 1 downto 0);
RESULT : out std_Logic_vector(A_Size + B_Size - 1 downto 0)
);
end SHIFT_MULT;
architecture rtl of SHIFT_MULT is
signal A_SHREG : std_logic_vector(A_Size + B_Size - 1 downto 0);
signal B_SHREG : std_logic_vector(B_Size - 1 downto 0);
signal ADDER : std_logic_vector(A_Size + B_Size - 1 downto 0);
signal ADDER_CE : std_logic;
signal RES_TRIGGER : std_logic;
Function ORer(MyVector : std_logic_vector) return std_logic is
Variable MyResult : std_logic;
Begin
MyResult := '0';
For i in MyVector'Range loop
MyResult := MyResult or MyVector(i);
End loop;
return MyResult;
End;
begin
-- shift registers
process(RESET, CLOCK)
begin
if RESET = '1' then
A_SHREG <= (others => '0');
B_SHREG <= (others => '0');
elsif rising_edge(CLOCK) then
if LOAD = '1' then
A_SHREG <= sxt(A, A_Size + B_Size);
B_SHREG <= B;
else
A_SHREG <= A_SHREG(A_Size + B_Size - 2 downto 0) & '0';
B_SHREG <= '0' & B_SHREG(B_Size - 1 downto 1);
end if;
end if;
end process;
ADDER_CE <= B_SHREG(0);
RES_TRIGGER <= ORer(B_SHREG);
-- adder
process(RESET, CLOCK)
begin
if RESET = '1' then
ADDER <= (others => '0');
elsif rising_edge(CLOCK) then
if LOAD = '1' then
ADDER <= (others => '0');
elsif ADDER_CE = '1' then
ADDER <= ADDER + A_SHREG;
end if;
end if;
end process;
-- Result Flag
process(RESET, CLOCK)
begin
if RESET = '1' then
RESULT <= (others => '0');
elsif rising_edge(CLOCK) then
if RES_TRIGGER = '0' then
RESULT <= ADDER;
end if;
end if;
end process;
------------------------------
-- Best wishes,
------ Pavel Matyushin
------------------------------
end rtl;
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