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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_level is
generic (adress_length:integer:=12);
Port (
-- INPUTS!
-- Adress Ports
sa_in: in std_logic_vector(adress_length-1 downto 0);
-- END PORTS
);
-- LOCATIONS
attribute loc: string;
error=> attribute loc of sa_in(0): signal is "P39";
attribute loc of sa_in(1): signal is "P40";
attribute loc of sa_in(2): signal is "P41";
attribute loc of sa_in(3): signal is "P42";
attribute loc of sa_in(4): signal is "P43";
attribute loc of sa_in(5): signal is "P44";
attribute loc of sa_in(6): signal is "P1";
attribute loc of sa_in(7): signal is "P2";
attribute loc of sa_in(8): signal is "P3";
attribute loc of sa_in(9): signal is "P5";
attribute loc of sa_in(10): signal is "P6";
attribute loc of sa_in(11): signal is "P7";
...
ERROR:HDLParsers:164 - C:/Xilinx_WebPack/bin/rs485_fullVHDL/top_level.vhd Line 110. parse error, unexpected OPENPAR, expecting COLON
этот жук ругается на строку где написано еррор, что разве нельзя так вектор разбить ?
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